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21 lines
691 B
TableGen
21 lines
691 B
TableGen
//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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/// General Purpose Registers: W, X.
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def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
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/// Floating Point/Vector Registers: B, H, S, D, Q.
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def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
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/// Conditional register: NZCV.
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def CCRegBank : RegisterBank<"CC", [CCR]>;
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