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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
44 lines
1.0 KiB
LLVM
44 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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; CHECK: fmov s0, w0
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; CHECK: cnt.8b v0, v0
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; CHECK: uaddlv.8b h0, v0
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; CHECK: fmov w0, s0
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; CHECK: ret
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}
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define i64 @cnt64_advsimd(i64 %x) nounwind readnone {
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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; CHECK: fmov d0, x0
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; CHECK: cnt.8b v0, v0
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; CHECK: uaddlv.8b h0, v0
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; CHECK: fmov w0, s0
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; CHECK: ret
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}
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; Do not use AdvSIMD when -mno-implicit-float is specified.
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; rdar://9473858
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define i32 @cnt32(i32 %x) nounwind readnone noimplicitfloat {
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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; CHECK-LABEL: cnt32:
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; CHECK-NOT 16b
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; CHECK: ret
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}
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define i64 @cnt64(i64 %x) nounwind readnone noimplicitfloat {
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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; CHECK-LABEL: cnt64:
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; CHECK-NOT 16b
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; CHECK: ret
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}
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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