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https://github.com/RPCS3/llvm-mirror.git
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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
69 lines
2.7 KiB
LLVM
69 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <2 x float> @f1(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
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; CHECK: fmaxnm.2s v0, v0, v1
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; CHECK: ret
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%vmaxnm2.i = tail call <2 x float> @llvm.arm64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
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ret <2 x float> %vmaxnm2.i
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}
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define <4 x float> @f2(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
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; CHECK: fmaxnm.4s v0, v0, v1
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; CHECK: ret
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%vmaxnm2.i = tail call <4 x float> @llvm.arm64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
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ret <4 x float> %vmaxnm2.i
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}
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define <2 x double> @f3(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
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; CHECK: fmaxnm.2d v0, v0, v1
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; CHECK: ret
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%vmaxnm2.i = tail call <2 x double> @llvm.arm64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
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ret <2 x double> %vmaxnm2.i
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}
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define <2 x float> @f4(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
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; CHECK: fminnm.2s v0, v0, v1
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; CHECK: ret
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%vminnm2.i = tail call <2 x float> @llvm.arm64.neon.fminnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
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ret <2 x float> %vminnm2.i
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}
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define <4 x float> @f5(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
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; CHECK: fminnm.4s v0, v0, v1
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; CHECK: ret
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%vminnm2.i = tail call <4 x float> @llvm.arm64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
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ret <4 x float> %vminnm2.i
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}
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define <2 x double> @f6(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
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; CHECK: fminnm.2d v0, v0, v1
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; CHECK: ret
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%vminnm2.i = tail call <2 x double> @llvm.arm64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
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ret <2 x double> %vminnm2.i
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}
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declare <2 x double> @llvm.arm64.neon.fminnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
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declare <4 x float> @llvm.arm64.neon.fminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x float> @llvm.arm64.neon.fminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <2 x double> @llvm.arm64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
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declare <4 x float> @llvm.arm64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x float> @llvm.arm64.neon.fmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define double @test_fmaxnmv(<2 x double> %in) {
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; CHECK-LABEL: test_fmaxnmv:
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; CHECK: fmaxnmp.2d d0, v0
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%max = call double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
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ret double %max
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}
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define double @test_fminnmv(<2 x double> %in) {
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; CHECK-LABEL: test_fminnmv:
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; CHECK: fminnmp.2d d0, v0
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%min = call double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double> %in)
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ret double %min
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}
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declare double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double>)
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declare double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double>)
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