..
AArch64
[RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs
2021-07-14 04:29:42 -07:00
AMDGPU
GlobalISel: Handle lowering non-power-of-2 extloads
2021-07-14 11:54:11 -04:00
ARC
ARM
ARM: reuse existing libcall global variable if possible.
2021-07-14 14:14:47 +01:00
AVR
Place the BlockAddress type in the address space of the containing function
2021-07-02 12:17:55 +01:00
BPF
[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (REAPPLIED)
2021-07-14 12:21:01 +01:00
Generic
[llc] Default MCUseDwarfDirectory to true
2021-07-12 17:44:02 -07:00
Hexagon
[DAG] Reassociate Add with Or
2021-07-07 10:21:07 +01:00
Inputs
Lanai
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
M68k
[M68k][GloballSel] Lower outgoing return values in IRTranslator
2021-07-05 11:39:09 -07:00
Mips
Mips/GlobalISel: Use more standard call lowering infrastructure
2021-07-13 11:04:10 -04:00
MIR
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
MSP430
NVPTX
tests/CodeGen: Use %python lit substitution when invoking python
2021-07-06 18:46:36 -07:00
PowerPC
[AIX] Enable dollar sign as PC in inlineasm
2021-07-14 13:37:52 +00:00
RISCV
[RISCV] Fix the neutral element in vector 'fadd' reductions
2021-07-14 10:18:38 +01:00
SPARC
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
SystemZ
[SystemZ] Bugfix for the 'N' code for inline asm operand.
2021-07-12 15:04:08 +02:00
Thumb
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
Thumb2
[ARM] Lower v16i8 -> i64 VMLA reductions.
2021-07-14 18:11:32 +01:00
VE
WebAssembly
[WebAssembly] Codegen for v128.loadX_lane instructions
2021-07-14 11:31:53 -07:00
WinCFGuard
WinEH
X86
[RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs
2021-07-14 04:29:42 -07:00
XCore