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Part 1 was submitted in http://reviews.llvm.org/D15134. Changes in this part: * X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class. * X86CallingConv.td: Pass f128 values in XMM registers or on stack. * X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td: Add instruction selection patterns for f128. * X86ISelLowering.cpp: When target has MMX registers, configure MVT::f128 in FR128RegClass, with TypeSoftenFloat action, and custom actions for some opcodes. Add missed cases of MVT::f128 in places that handle f32, f64, or vector types. Add TODO comment to support f128 type in inline assembly code. * SelectionDAGBuilder.cpp: Fix infinite loop when f128 type can have VT == TLI.getTypeToTransformTo(Ctx, VT). * Add unit tests for x86-64 fp128 type. Differential Revision: http://reviews.llvm.org/D11438 llvm-svn: 255558
36 lines
1.2 KiB
LLVM
36 lines
1.2 KiB
LLVM
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx | FileCheck %s
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx | FileCheck %s
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; __float128 myFP128 = 1.0L; // x86_64-linux-android
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@my_fp128 = global fp128 0xL00000000000000003FFF000000000000, align 16
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define fp128 @get_fp128() {
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entry:
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%0 = load fp128, fp128* @my_fp128, align 16
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ret fp128 %0
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; CHECK-LABEL: get_fp128:
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; CHECK: movaps my_fp128(%rip), %xmm0
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; CHECK-NEXT: retq
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}
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@TestLoadExtend.data = internal unnamed_addr constant [2 x float] [float 0x3FB99999A0000000, float 0x3FC99999A0000000], align 4
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define fp128 @TestLoadExtend(fp128 %x, i32 %n) {
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entry:
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%idxprom = sext i32 %n to i64
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%arrayidx = getelementptr inbounds [2 x float], [2 x float]* @TestLoadExtend.data, i64 0, i64 %idxprom
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%0 = load float, float* %arrayidx, align 4
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%conv = fpext float %0 to fp128
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ret fp128 %conv
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; CHECK-LABEL: TestLoadExtend:
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; CHECK: movslq %edi, %rax
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; CHECK-NEXT: movss TestLoadExtend.data(,%rax,4), %xmm0
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; CHECK-NEXT: callq __extendsftf2
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; CHECK: retq
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}
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; CHECK-LABEL: my_fp128:
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; CHECK-NEXT: .quad 0
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; CHECK-NEXT: .quad 4611404543450677248
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; CHECK-NEXT: .size my_fp128, 16
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