mirror of
https://github.com/RPCS3/llvm-mirror.git
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7b7d569297
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
94 lines
1.9 KiB
LLVM
94 lines
1.9 KiB
LLVM
; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s
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define i8 @add8_reg_reg(i8 %a, i8 %b) {
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; CHECK-LABEL: add8_reg_reg:
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; CHECK: add r24, r22
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%result = add i8 %a, %b
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ret i8 %result
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}
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define i8 @add8_reg_imm(i8 %a) {
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; CHECK-LABEL: add8_reg_imm:
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; CHECK: subi r24, -5
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%result = add i8 %a, 5
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ret i8 %result
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}
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define i8 @add8_reg_increment(i8 %a) {
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; CHECK-LABEL: add8_reg_increment:
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; CHECK: inc r24
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%result = add i8 %a, 1
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ret i8 %result
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}
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define i16 @add16_reg_reg(i16 %a, i16 %b) {
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; CHECK-LABEL: add16_reg_reg:
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; CHECK: add r24, r22
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; CHECK: adc r25, r23
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%result = add i16 %a, %b
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ret i16 %result
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}
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define i16 @add16_reg_imm(i16 %a) {
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; CHECK-LABEL: add16_reg_imm:
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; CHECK: adiw r24, 63
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%result = add i16 %a, 63
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ret i16 %result
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}
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define i16 @add16_reg_imm_subi(i16 %a) {
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; CHECK-LABEL: add16_reg_imm_subi:
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; CHECK: subi r24, 133
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; CHECK: sbci r25, 255
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%result = add i16 %a, 123
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ret i16 %result
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}
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define i32 @add32_reg_reg(i32 %a, i32 %b) {
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; CHECK-LABEL: add32_reg_reg:
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; CHECK: add r22, r18
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; CHECK: adc r23, r19
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; CHECK: adc r24, r20
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; CHECK: adc r25, r21
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%result = add i32 %a, %b
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ret i32 %result
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}
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define i32 @add32_reg_imm(i32 %a) {
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; CHECK-LABEL: add32_reg_imm:
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; CHECK: subi r22, 251
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; CHECK: sbci r23, 255
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; CHECK: sbci r24, 255
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; CHECK: sbci r25, 255
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%result = add i32 %a, 5
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ret i32 %result
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}
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define i64 @add64_reg_reg(i64 %a, i64 %b) {
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; CHECK-LABEL: add64_reg_reg:
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; CHECK: add r18, r10
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; CHECK: adc r20, r12
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; CHECK: adc r21, r13
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; CHECK: adc r22, r14
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; CHECK: adc r23, r15
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; CHECK: adc r24, r16
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; CHECK: adc r25, r17
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%result = add i64 %a, %b
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ret i64 %result
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}
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define i64 @add64_reg_imm(i64 %a) {
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; CHECK-LABEL: add64_reg_imm:
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; CHECK: subi r18, 251
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; CHECK: sbci r19, 255
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; CHECK: sbci r20, 255
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; CHECK: sbci r21, 255
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; CHECK: sbci r22, 255
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; CHECK: sbci r23, 255
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; CHECK: sbci r24, 255
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; CHECK: sbci r25, 255
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%result = add i64 %a, 5
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ret i64 %result
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}
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