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b3a8585bc1
`llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. This patch: - Removes -march if the .ll file already has a matching `target triple` directive or -mtriple argument. - In all other cases changes -march=ppc32/-march=ppc64 to -mtriple=ppc32--/-mtriple=ppc64-- See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309754
52 lines
1.4 KiB
LLVM
52 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32-NOFP
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-FP
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin8 | FileCheck %s -check-prefix=PPC64-NOFP
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-FP
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define i32* @f1() nounwind {
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%tmp = alloca i32, i32 8191 ; <i32*> [#uses=1]
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ret i32* %tmp
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}
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; PPC32-NOFP: _f1:
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; PPC32-NOFP: lis r0, -1
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; PPC32-NOFP: ori r0, r0, 32736
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; PPC32-NOFP: stwux r1, r1, r0
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; PPC32-NOFP: addi r3, r1, 36
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; PPC32-NOFP: lwz r1, 0(r1)
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; PPC32-NOFP: blr
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; PPC32-FP: _f1:
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; PPC32-FP: lis r0, -1
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; PPC32-FP: stw r31, -4(r1)
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; PPC32-FP: ori r0, r0, 32736
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; PPC32-FP: stwux r1, r1, r0
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; PPC32-FP: mr r31, r1
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; PPC32-FP: addi r3, r31, 32
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; PPC32-FP: lwz r1, 0(r1)
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; PPC32-FP: lwz r31, -4(r1)
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; PPC32-FP: blr
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; PPC64-NOFP: _f1:
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; PPC64-NOFP: lis r0, -1
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; PPC64-NOFP: ori r0, r0, 32720
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; PPC64-NOFP: stdux r1, r1, r0
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; PPC64-NOFP: addi r3, r1, 52
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; PPC64-NOFP: ld r1, 0(r1)
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; PPC64-NOFP: blr
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; PPC64-FP: _f1:
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; PPC64-FP: lis r0, -1
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; PPC64-FP: std r31, -8(r1)
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; PPC64-FP: ori r0, r0, 32704
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; PPC64-FP: stdux r1, r1, r0
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; PPC64-FP: mr r31, r1
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; PPC64-FP: addi r3, r31, 60
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; PPC64-FP: ld r1, 0(r1)
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; PPC64-FP: ld r31, -8(r1)
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; PPC64-FP: blr
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