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llvm-mirror/test/CodeGen/X86/slow-incdec.ll
Craig Topper d87f426279 [X86] Don't disable slow INC/DEC if optimizing for size
Summary:
Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size.

This appears to match gcc behavior.

Reviewers: chandlerc, zvi, RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37177

llvm-svn: 312866
2017-09-09 17:11:59 +00:00

56 lines
1.4 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=-slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=INCDEC %s
; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=+slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=ADD %s
define i32 @inc(i32 %x) {
; INCDEC-LABEL: inc:
; INCDEC: # BB#0:
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: incl %eax
; INCDEC-NEXT: retl
;
; ADD-LABEL: inc:
; ADD: # BB#0:
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $1, %eax
; ADD-NEXT: retl
%r = add i32 %x, 1
ret i32 %r
}
define i32 @dec(i32 %x) {
; INCDEC-LABEL: dec:
; INCDEC: # BB#0:
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: decl %eax
; INCDEC-NEXT: retl
;
; ADD-LABEL: dec:
; ADD: # BB#0:
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $-1, %eax
; ADD-NEXT: retl
%r = add i32 %x, -1
ret i32 %r
}
define i32 @inc_size(i32 %x) optsize {
; CHECK-LABEL: inc_size:
; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: incl %eax
; CHECK-NEXT: retl
%r = add i32 %x, 1
ret i32 %r
}
define i32 @dec_size(i32 %x) optsize {
; CHECK-LABEL: dec_size:
; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: decl %eax
; CHECK-NEXT: retl
%r = add i32 %x, -1
ret i32 %r
}