1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 02:33:06 +01:00
llvm-mirror/lib/MCA
Andrea Di Biagio ba5ec98548 [MCA][RegisterFile] Fix register class check for move elimination (PR50265)
The register file should always check if the destination register is from a
register class that allows move elimination.

Before this change, the check on the register class was only performed in a few
very specific cases. However, it should have always been performed.
This patch fixes the issue.

Note that none of the upstream scheduling models is currently affected by this
bug, so there is no test for it. The issue was found by Roman while working on
the znver3 model. I was able to reproduce the issue locally by tweaking the
btver2 model. I then verified that this patch fixes the issue.
2021-05-07 21:30:25 +01:00
..
HardwareUnits [MCA][RegisterFile] Fix register class check for move elimination (PR50265) 2021-05-07 21:30:25 +01:00
Stages [MCA] Fix CarryOver check in the DispatchStage (PR50174). 2021-04-30 14:26:46 +01:00
CMakeLists.txt [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
CodeEmitter.cpp [MC][Bugfix] Remove redundant parameter for relaxInstruction 2020-04-21 11:06:55 +08:00
Context.cpp [MCA] Disable RCU for InOrderIssueStage 2021-03-24 13:54:04 +03:00
HWEventListener.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
InstrBuilder.cpp [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
Instruction.cpp [MCA] Improved handling of negative read-advance cycles. 2021-03-23 14:47:23 +00:00
Pipeline.cpp Revert "Remove redundant "std::move"s in return statements" 2020-02-10 07:07:40 -08:00
Support.cpp [MCA] Improved debug prints. NFC 2019-02-12 16:18:57 +00:00