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051f2ef225
This patch adds the PseudoCALLReg instruction which allows using an explicit register operand as the destination for the return address. GCC can successfully parse this form of the call instruction, which would be used for calls to functions which do not use ra as the return address register, such as the __riscv_save libcalls. This patch forms the first part of an implementation of -msave-restore for RISC-V. Differential Revision: https://reviews.llvm.org/D62685 llvm-svn: 364403
68 lines
1.8 KiB
ArmAsm
68 lines
1.8 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
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# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
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# RUN: | FileCheck -check-prefix=FIXUP %s
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.long foo
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call foo
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# RELOC: R_RISCV_CALL foo 0x0
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# INSTR: auipc ra, 0
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# INSTR: jalr ra
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# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call
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call bar
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# RELOC: R_RISCV_CALL bar 0x0
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# INSTR: auipc ra, 0
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# INSTR: jalr ra
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# FIXUP: fixup A - offset: 0, value: bar, kind: fixup_riscv_call
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# Ensure that calls to functions whose names coincide with register names work.
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call zero
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# RELOC: R_RISCV_CALL zero 0x0
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# INSTR: auipc ra, 0
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# INSTR: jalr ra
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# FIXUP: fixup A - offset: 0, value: zero, kind: fixup_riscv_call
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call f1
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# RELOC: R_RISCV_CALL f1 0x0
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# INSTR: auipc ra, 0
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# INSTR: jalr ra
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# FIXUP: fixup A - offset: 0, value: f1, kind: fixup_riscv_call
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call ra
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# RELOC: R_RISCV_CALL ra 0x0
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# INSTR: auipc ra, 0
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# INSTR: jalr ra
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# FIXUP: fixup A - offset: 0, value: ra, kind: fixup_riscv_call
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call mstatus
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# RELOC: R_RISCV_CALL mstatus 0x0
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# INSTR: auipc ra, 0
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# INSTR: jalr ra
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# FIXUP: fixup A - offset: 0, value: mstatus, kind: fixup_riscv_call
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# Ensure that calls to procedure linkage table symbols work.
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call foo@plt
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# RELOC: R_RISCV_CALL_PLT foo 0x0
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# INSTR: auipc ra, 0
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# INSTR: jalr ra
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# FIXUP: fixup A - offset: 0, value: foo@plt, kind: fixup_riscv_call_plt
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# Ensure that an explicit register operand can be parsed.
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call a0, foo
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# RELOC: R_RISCV_CALL foo 0x0
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# INSTR: auipc a0, 0
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# INSTR: jalr a0
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# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call
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call a0, foo@plt
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# RELOC: R_RISCV_CALL_PLT foo 0x0
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# INSTR: auipc a0, 0
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# INSTR: jalr a0
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# FIXUP: fixup A - offset: 0, value: foo@plt, kind: fixup_riscv_call_plt
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