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762c21ab09
This is required because empty strings are not allowed when generating the assembly parser tables. Differential Revision: https://reviews.llvm.org/D98532
713 lines
30 KiB
TableGen
713 lines
30 KiB
TableGen
//== M68kInstrData.td - M68k Data Movement Instructions -*- tablegen --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes the Motorola 680x0 data movement instructions which are
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/// the basic means of transferring and storing addresses and data. Here is the
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/// current status of the file:
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///
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/// Machine:
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///
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/// EXG [ ] FMOVE [ ] FSMOVE [ ] FDMOVE [ ] FMOVEM [ ]
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/// LEA [~] PEA [ ] MOVE [~] MOVE16 [ ] MOVEA [ ]
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/// MOVEM [ ] MOVEP [ ] MOVEQ [ ] LINK [ ] UNLK [ ]
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///
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/// Pseudo:
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///
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/// MOVSX [x] MOVZX [x] MOVX [x]
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///
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/// Map:
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///
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/// [ ] - was not touched at all
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/// [!] - requires extarnal stuff implemented
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/// [~] - in progress but usable
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/// [x] - done
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MOVE
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//===----------------------------------------------------------------------===//
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/// -----------------------------------------------------
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/// F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
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/// -----------------------------------------------------
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/// | | DESTINATION | SOURCE
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/// 0 0 | SIZE | REG | MODE | MODE | REG
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/// -----------------------------------------------------
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///
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/// NOTE Move requires EA X version for direct register destination(0)
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class MxMoveEncoding<MxBead2Bits size,
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MxEncEA srcEA, MxEncExt srcExt,
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MxEncEA dstEA, MxEncExt dstExt>
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: MxEncoding<srcEA.Reg, srcEA.DA, srcEA.Mode, dstEA.DA, dstEA.Mode, dstEA.Reg,
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size, MxBead2Bits<0b00>,
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srcExt.Imm, srcExt.B8, srcExt.Scale, srcExt.WL, srcExt.DAReg,
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dstExt.Imm, dstExt.B8, dstExt.Scale, dstExt.WL, dstExt.DAReg>;
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/// MOVE has alternate size encoding
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class MxMoveSize<bits<2> value> : MxBead2Bits<value>;
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def MxMoveSize8 : MxMoveSize<0b01>;
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def MxMoveSize16 : MxMoveSize<0b11>;
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def MxMoveSize32 : MxMoveSize<0b10>;
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let Defs = [CCR] in
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class MxMove<string size, dag outs, dag ins, list<dag> pattern, MxEncoding enc>
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: MxInst<outs, ins, "move."#size#"\t$src, $dst", pattern, enc>;
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class MxMove_RR<MxType DST, MxType SRC, MxMoveEncoding ENC>
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: MxMove<DST.Prefix, (outs DST.ROp:$dst), (ins SRC.ROp:$src),
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[(null_frag)], ENC>;
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let mayStore = 1 in {
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class MxMove_MR<MxOperand MEMOpd, ComplexPattern MEMPat, MxType REG,
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MxMoveEncoding ENC>
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: MxMove<REG.Prefix, (outs), (ins MEMOpd:$dst, REG.ROp:$src),
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[(store REG.VT:$src, MEMPat:$dst)], ENC>;
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class MxMove_MI<MxOperand MEMOpd, ComplexPattern MEMPat, MxType TYPE,
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MxMoveEncoding ENC>
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: MxMove<TYPE.Prefix, (outs), (ins MEMOpd:$dst, TYPE.IOp:$src),
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[(store TYPE.IPat:$src, MEMPat:$dst)], ENC>;
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} // let mayStore = 1
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class MxMove_RI<MxType DST, MxMoveEncoding ENC>
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: MxMove<DST.Prefix, (outs DST.ROp:$dst), (ins DST.IOp:$src),
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[(set DST.VT:$dst, DST.IPat:$src)], ENC>;
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let mayLoad = 1 in
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class MxMove_RM<MxType REG, MxOperand MEMOpd, ComplexPattern MEMPat,
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MxBead2Bits SIZE,
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MxEncEA SRCEA, MxEncExt SRCEXT,
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MxEncEA DSTEA, MxEncExt DSTEXT>
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: MxMove<REG.Prefix, (outs REG.ROp:$dst), (ins MEMOpd:$src),
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[(set REG.VT:$dst, (REG.Load MEMPat:$src))],
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MxMoveEncoding<SIZE, SRCEA, SRCEXT, DSTEA, DSTEXT>>;
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multiclass MMxMove_RM<MxType REG, MxMoveSize SIZE, MxEncEA EA_0> {
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// REG <- (An)+
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def NAME#REG.OOp.Letter#REG.Postfix : MxMove_RM<REG, REG.OOp, REG.OPat,
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SIZE, MxEncEAo_1, MxExtEmpty, EA_0, MxExtEmpty>;
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// REG <- -(An)
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def NAME#REG.EOp.Letter#REG.Postfix : MxMove_RM<REG, REG.EOp, REG.EPat,
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SIZE, MxEncEAe_1, MxExtEmpty, EA_0, MxExtEmpty>;
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// REG <- (i,PC,Xn)
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def NAME#REG.KOp.Letter#REG.Postfix : MxMove_RM<REG, REG.KOp, REG.KPat,
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SIZE, MxEncEAk, MxExtBrief_1, EA_0, MxExtEmpty>;
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// REG <- (i,PC)
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def NAME#REG.QOp.Letter#REG.Postfix : MxMove_RM<REG, REG.QOp, REG.QPat,
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SIZE, MxEncEAq, MxExtI16_1, EA_0, MxExtEmpty>;
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// REG <- (i,An,Xn)
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def NAME#REG.FOp.Letter#REG.Postfix : MxMove_RM<REG, REG.FOp, REG.FPat,
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SIZE, MxEncEAf_1, MxExtBrief_1, EA_0, MxExtEmpty>;
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// REG <- (i,An)
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def NAME#REG.POp.Letter#REG.Postfix : MxMove_RM<REG, REG.POp, REG.PPat,
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SIZE, MxEncEAp_1, MxExtI16_1, EA_0, MxExtEmpty>;
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// REG <- (ABS)
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def NAME#REG.BOp.Letter#REG.Postfix : MxMove_RM<REG, REG.BOp, REG.BPat,
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SIZE, MxEncEAb, MxExtI32_1, EA_0, MxExtEmpty>;
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// REG <- (An)
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def NAME#REG.JOp.Letter#REG.Postfix : MxMove_RM<REG, REG.JOp, REG.JPat,
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SIZE, MxEncEAj_1, MxExtEmpty, EA_0, MxExtEmpty>;
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}
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let mayLoad = 1, mayStore = 1 in {
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class MxMove_MM<string SIZE, PatFrag LOAD,
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MxOperand DSTOpd, ComplexPattern DSTPat,
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MxOperand SRCOpd, ComplexPattern SRCPat,
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MxBead2Bits ESIZE,
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MxEncEA SRCEA, MxEncExt SRCEXT,
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MxEncEA DSTEA, MxEncExt DSTEXT>
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: MxMove<SIZE, (outs), (ins DSTOpd:$dst, SRCOpd:$src),
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[(store (LOAD SRCPat:$src), DSTPat:$dst)],
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MxMoveEncoding<ESIZE, SRCEA, SRCEXT, DSTEA, DSTEXT>>;
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} // let mayLoad = 1, mayStore = 1
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multiclass MMxMove_MM<MxType TYPE, MxOperand DSTOpd, ComplexPattern DSTPat,
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MxMoveSize SIZE, MxEncEA EA_0, MxEncExt EXT_0> {
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// MEM <- (An)+
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def NAME#TYPE.OOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.OOp, TYPE.OPat,
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SIZE, MxEncEAo_1, MxExtEmpty, EA_0, EXT_0>;
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// MEM <- -(An)
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def NAME#TYPE.EOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.EOp, TYPE.EPat,
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SIZE, MxEncEAe_1, MxExtEmpty, EA_0, EXT_0>;
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// MEM <- (i,An)
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def NAME#TYPE.POp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.POp, TYPE.PPat,
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SIZE, MxEncEAp_1, MxExtI16_1, EA_0, EXT_0>;
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// MEM <- (i,An,Xn)
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def NAME#TYPE.FOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.FOp, TYPE.FPat,
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SIZE, MxEncEAf_1, MxExtBrief_1, EA_0, EXT_0>;
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// MEM <- (i,PC,Xn)
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def NAME#TYPE.KOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.KOp, TYPE.KPat,
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SIZE, MxEncEAk, MxExtBrief_1, EA_0, EXT_0>;
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// MEM <- (i,PC)
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def NAME#TYPE.QOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.QOp, TYPE.QPat,
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SIZE, MxEncEAq, MxExtI16_1, EA_0, EXT_0>;
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// MEM <- (ABS)
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def NAME#TYPE.BOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.BOp, TYPE.BPat,
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SIZE, MxEncEAb, MxExtI32_1, EA_0, EXT_0>;
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// MEM <- (An)
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def NAME#TYPE.JOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.JOp, TYPE.JPat,
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SIZE, MxEncEAj_1, MxExtEmpty, EA_0, EXT_0>;
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}
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def MOV8dd
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: MxMove_RR<MxType8d, MxType8d,
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MxMoveEncoding<MxMoveSize8, MxEncEAd_1, MxExtEmpty, MxEncEAd_0, MxExtEmpty>>;
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// M <- R
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def MOV8fd : MxMove_MR<MxType8.FOp, MxType8.FPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAf_0, MxExtBrief_0>>;
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def MOV8pd : MxMove_MR<MxType8.POp, MxType8.PPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAp_0, MxExtI16_0>>;
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def MOV8ed : MxMove_MR<MxType8.EOp, MxType8.EPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAe_0, MxExtEmpty>>;
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def MOV8od : MxMove_MR<MxType8.OOp, MxType8.OPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAo_0, MxExtEmpty>>;
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def MOV8bd : MxMove_MR<MxType8.BOp, MxType8.BPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAb, MxExtI32_0>>;
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def MOV8jd : MxMove_MR<MxType8.JOp, MxType8.JPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAj_0, MxExtEmpty>>;
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// R <- I
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def MOV8di : MxMove_RI<MxType8d,
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MxMoveEncoding<MxMoveSize8, MxEncEAi, MxExtI8_1, MxEncEAd_0, MxExtEmpty>>;
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foreach S = [16, 32] in {
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foreach D = [ "r", "a" ] in {
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foreach O = [ "r", "a" ] in {
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def MOV#S#D#O : MxMove_RR<
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!cast<MxType>("MxType"#S#D),
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!cast<MxType>("MxType"#S#O),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
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!cast<MxEncEA>("MxEncEA"#D#"_0_reflected"), MxExtEmpty>>;
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}
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// M <- R
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def MOV#S#"f"#D : MxMove_MR<
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!cast<MxType>("MxType"#S).FOp,
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!cast<MxType>("MxType"#S).FPat,
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!cast<MxType>("MxType"#S#D),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
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MxEncEAf_0, MxExtBrief_0>>;
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def MOV#S#"p"#D : MxMove_MR<
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!cast<MxType>("MxType"#S).POp,
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!cast<MxType>("MxType"#S).PPat,
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!cast<MxType>("MxType"#S#D),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
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MxEncEAp_0, MxExtI16_0>>;
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def MOV#S#"e"#D : MxMove_MR<
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!cast<MxType>("MxType"#S).EOp,
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!cast<MxType>("MxType"#S).EPat,
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!cast<MxType>("MxType"#S#D),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
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MxEncEAe_0, MxExtEmpty>>;
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def MOV#S#"o"#D : MxMove_MR<
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!cast<MxType>("MxType"#S).OOp,
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!cast<MxType>("MxType"#S).OPat,
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!cast<MxType>("MxType"#S#D),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
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MxEncEAo_0, MxExtEmpty>>;
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def MOV#S#"b"#D : MxMove_MR<
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!cast<MxType>("MxType"#S).BOp,
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!cast<MxType>("MxType"#S).BPat,
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!cast<MxType>("MxType"#S#D),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
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MxEncEAb, MxExtI32_0>>;
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def MOV#S#"j"#D : MxMove_MR<
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!cast<MxType>("MxType"#S).JOp,
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!cast<MxType>("MxType"#S).JPat,
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!cast<MxType>("MxType"#S#D),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
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MxEncEAj_0, MxExtEmpty>>;
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// R <- I
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def MOV#S#D#"i" : MxMove_RI<
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!cast<MxType>("MxType"#S#D),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
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!cast<MxEncEA>("MxEncEA"#D#"_0_reflected"), MxExtEmpty>>;
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}
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}
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// M <- I
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foreach S = [8, 16, 32] in {
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def MOV#S#"f"#"i" : MxMove_MI<
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!cast<MxType>("MxType"#S).FOp,
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!cast<MxType>("MxType"#S).FPat,
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!cast<MxType>("MxType"#S),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
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MxEncEAf_0, MxExtBrief_0>>;
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def MOV#S#"p"#"i" : MxMove_MI<
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!cast<MxType>("MxType"#S).POp,
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!cast<MxType>("MxType"#S).PPat,
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!cast<MxType>("MxType"#S),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
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MxEncEAp_0, MxExtI16_0>>;
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def MOV#S#"b"#"i" : MxMove_MI<
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!cast<MxType>("MxType"#S).BOp,
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!cast<MxType>("MxType"#S).BPat,
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!cast<MxType>("MxType"#S),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
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MxEncEAb, MxExtI32_0>>;
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def MOV#S#"j"#"i" : MxMove_MI<
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!cast<MxType>("MxType"#S).JOp,
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!cast<MxType>("MxType"#S).JPat,
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!cast<MxType>("MxType"#S),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
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MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
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MxEncEAj_0, MxExtEmpty>>;
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}
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// Store ABS(basically pointer) as Immdiate to Mem
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def : Pat<(store MxType32.BPat :$src, MxType32.PPat :$dst),
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(MOV32pi MxType32.POp :$dst, MxType32.IOp :$src)>;
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def : Pat<(store MxType32.BPat :$src, MxType32.FPat :$dst),
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(MOV32fi MxType32.FOp :$dst, MxType32.IOp :$src)>;
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def : Pat<(store MxType32.BPat :$src, MxType32.BPat :$dst),
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(MOV32bi MxType32.BOp :$dst, MxType32.IOp :$src)>;
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def : Pat<(store MxType32.BPat :$src, MxType32.JPat :$dst),
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(MOV32ji MxType32.JOp :$dst, MxType32.IOp :$src)>;
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// R <- M
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defm MOV8d : MMxMove_RM<MxType8d, MxMoveSize8, MxEncEAd_0>;
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defm MOV16r : MMxMove_RM<MxType16r, MxMoveSize16, MxEncEAr_0_reflected>;
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defm MOV16a : MMxMove_RM<MxType16a, MxMoveSize16, MxEncEAa_0>;
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defm MOV32r : MMxMove_RM<MxType32r, MxMoveSize32, MxEncEAr_0_reflected>;
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defm MOV32a : MMxMove_RM<MxType32a, MxMoveSize32, MxEncEAa_0>;
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let Pattern = [(null_frag)] in {
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defm MOV16r : MMxMove_RM<MxType16r_TC, MxMoveSize16, MxEncEAr_0_reflected>;
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defm MOV16a : MMxMove_RM<MxType16a_TC, MxMoveSize16, MxEncEAa_0>;
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defm MOV32r : MMxMove_RM<MxType32r_TC, MxMoveSize32, MxEncEAr_0_reflected>;
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defm MOV32a : MMxMove_RM<MxType32a_TC, MxMoveSize32, MxEncEAa_0>;
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} // Pattern
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// M <- M
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defm MOV8p : MMxMove_MM<MxType8, MxType8.POp, MxType8.PPat,
|
|
MxMoveSize8, MxEncEAp_0, MxExtI16_0>;
|
|
defm MOV16p : MMxMove_MM<MxType16, MxType16.POp, MxType16.PPat,
|
|
MxMoveSize16, MxEncEAp_0, MxExtI16_0>;
|
|
defm MOV32p : MMxMove_MM<MxType32, MxType32.POp, MxType32.PPat,
|
|
MxMoveSize32, MxEncEAp_0, MxExtI16_0>;
|
|
|
|
defm MOV8f : MMxMove_MM<MxType8, MxType8.FOp, MxType8.FPat,
|
|
MxMoveSize8, MxEncEAf_0, MxExtBrief_0>;
|
|
defm MOV16f : MMxMove_MM<MxType16, MxType16.FOp, MxType16.FPat,
|
|
MxMoveSize16, MxEncEAf_0, MxExtBrief_0>;
|
|
defm MOV32f : MMxMove_MM<MxType32, MxType32.FOp, MxType32.FPat,
|
|
MxMoveSize32, MxEncEAf_0, MxExtBrief_0>;
|
|
|
|
defm MOV8b : MMxMove_MM<MxType8, MxType8.BOp, MxType8.BPat,
|
|
MxMoveSize8, MxEncEAb, MxExtI32_0>;
|
|
defm MOV16b : MMxMove_MM<MxType16, MxType16.BOp, MxType16.BPat,
|
|
MxMoveSize16, MxEncEAb, MxExtI32_0>;
|
|
defm MOV32b : MMxMove_MM<MxType32, MxType32.BOp, MxType32.BPat,
|
|
MxMoveSize32, MxEncEAb, MxExtI32_0>;
|
|
|
|
defm MOV8e : MMxMove_MM<MxType8, MxType8.EOp, MxType8.EPat,
|
|
MxMoveSize8, MxEncEAe_0, MxExtEmpty>;
|
|
defm MOV16e : MMxMove_MM<MxType16, MxType16.EOp, MxType16.EPat,
|
|
MxMoveSize16, MxEncEAe_0, MxExtEmpty>;
|
|
defm MOV32e : MMxMove_MM<MxType32, MxType32.EOp, MxType32.EPat,
|
|
MxMoveSize32, MxEncEAe_0, MxExtEmpty>;
|
|
|
|
defm MOV8o : MMxMove_MM<MxType8, MxType8.OOp, MxType8.OPat,
|
|
MxMoveSize8, MxEncEAo_0, MxExtEmpty>;
|
|
defm MOV16o : MMxMove_MM<MxType16, MxType16.OOp, MxType16.OPat,
|
|
MxMoveSize16, MxEncEAo_0, MxExtEmpty>;
|
|
defm MOV32o : MMxMove_MM<MxType32, MxType32.OOp, MxType32.OPat,
|
|
MxMoveSize32, MxEncEAo_0, MxExtEmpty>;
|
|
|
|
defm MOV8j : MMxMove_MM<MxType8, MxType8.JOp, MxType8.JPat,
|
|
MxMoveSize8, MxEncEAj_0, MxExtEmpty>;
|
|
defm MOV16j : MMxMove_MM<MxType16, MxType16.JOp, MxType16.JPat,
|
|
MxMoveSize16, MxEncEAj_0, MxExtEmpty>;
|
|
defm MOV32j : MMxMove_MM<MxType32, MxType32.JOp, MxType32.JPat,
|
|
MxMoveSize32, MxEncEAj_0, MxExtEmpty>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MOVEM
|
|
//
|
|
// The mask is already pre-processed by the save/restore spill hook
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Direction
|
|
def MxMOVEM_MR : MxBead1Bit<0>;
|
|
def MxMOVEM_RM : MxBead1Bit<1>;
|
|
|
|
// Size
|
|
def MxMOVEM_W : MxBead1Bit<0>;
|
|
def MxMOVEM_L : MxBead1Bit<1>;
|
|
|
|
/// ---------------+-------------+-------------+---------
|
|
/// F E D C B | A | 9 8 7 | 6 | 5 4 3 | 2 1 0
|
|
/// ---------------+---+---------+---+---------+---------
|
|
/// 0 1 0 0 1 | D | 0 0 1 | S | MODE | REG
|
|
/// ---------------+---+---------+---+---------+---------
|
|
/// REGISTER LIST MASK
|
|
/// -----------------------------------------------------
|
|
/// D - direction(RM,MR)
|
|
/// S - size(W,L)
|
|
class MxMOVEMEncoding<MxEncEA EA, MxEncExt EXT, MxBead1Bit SIZE, MxBead1Bit DIR,
|
|
MxBead16Imm IMM>
|
|
: MxEncoding<EA.Reg, EA.DA, EA.Mode, SIZE, MxBead3Bits<0b001>, DIR,
|
|
MxBead1Bit<1>, MxBead4Bits<0b0100>, IMM,
|
|
EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
|
|
|
|
let mayStore = 1 in
|
|
class MxMOVEM_MR<MxType TYPE, MxBead1Bit SIZE,
|
|
MxOperand MEMOp, MxEncEA EA, MxEncExt EXT>
|
|
: MxInst<(outs), (ins MEMOp:$dst, MxMoveMask:$mask),
|
|
"movem."#TYPE.Prefix#"\t$mask, $dst", [],
|
|
MxMOVEMEncoding<EA, EXT, SIZE, MxMOVEM_MR, MxBead16Imm<1>>>;
|
|
|
|
let mayLoad = 1 in
|
|
class MxMOVEM_RM<MxType TYPE, MxBead1Bit SIZE,
|
|
MxOperand MEMOp, MxEncEA EA, MxEncExt EXT>
|
|
: MxInst<(outs), (ins MxMoveMask:$mask, MEMOp:$src),
|
|
"movem."#TYPE.Prefix#"\t$src, $mask", [],
|
|
MxMOVEMEncoding<EA, EXT, SIZE, MxMOVEM_RM, MxBead16Imm<0>>>;
|
|
|
|
def MOVM32jm : MxMOVEM_MR<MxType32, MxMOVEM_L, MxType32.JOp, MxEncEAj_0, MxExtEmpty>;
|
|
def MOVM32pm : MxMOVEM_MR<MxType32, MxMOVEM_L, MxType32.POp, MxEncEAp_0, MxExtI16_0>;
|
|
|
|
def MOVM32mj : MxMOVEM_RM<MxType32, MxMOVEM_L, MxType32.JOp, MxEncEAj_1, MxExtEmpty>;
|
|
def MOVM32mp : MxMOVEM_RM<MxType32, MxMOVEM_L, MxType32.POp, MxEncEAp_1, MxExtI16_1>;
|
|
|
|
// Pseudo versions. These a required by virtual register spill/restore since
|
|
// the mask requires real register to encode. These instruction will be expanded
|
|
// into real MOVEM after RA finishes.
|
|
let mayStore = 1 in
|
|
class MxMOVEM_MR_Pseudo<MxType TYPE, MxOperand MEMOp>
|
|
: MxPseudo<(outs), (ins MEMOp:$dst, TYPE.ROp:$reg)>;
|
|
let mayLoad = 1 in
|
|
class MxMOVEM_RM_Pseudo<MxType TYPE, MxOperand MEMOp>
|
|
: MxPseudo<(outs TYPE.ROp:$dst), (ins MEMOp:$src)>;
|
|
|
|
// Mem <- Reg
|
|
def MOVM8jm_P : MxMOVEM_MR_Pseudo<MxType8d, MxType8.JOp>;
|
|
def MOVM16jm_P : MxMOVEM_MR_Pseudo<MxType16r, MxType16.JOp>;
|
|
def MOVM32jm_P : MxMOVEM_MR_Pseudo<MxType32r, MxType32.JOp>;
|
|
|
|
def MOVM8pm_P : MxMOVEM_MR_Pseudo<MxType8d, MxType8.POp>;
|
|
def MOVM16pm_P : MxMOVEM_MR_Pseudo<MxType16r, MxType16.POp>;
|
|
def MOVM32pm_P : MxMOVEM_MR_Pseudo<MxType32r, MxType32.POp>;
|
|
|
|
// Reg <- Mem
|
|
def MOVM8mj_P : MxMOVEM_RM_Pseudo<MxType8d, MxType8.JOp>;
|
|
def MOVM16mj_P : MxMOVEM_RM_Pseudo<MxType16r, MxType16.JOp>;
|
|
def MOVM32mj_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.JOp>;
|
|
|
|
def MOVM8mp_P : MxMOVEM_RM_Pseudo<MxType8d, MxType8.POp>;
|
|
def MOVM16mp_P : MxMOVEM_RM_Pseudo<MxType16r, MxType16.POp>;
|
|
def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MOVE to/from SR/CCR
|
|
//
|
|
// A special care must be taken working with to/from CCR since it is basically
|
|
// word-size SR register truncated for user mode thus it only supports word-size
|
|
// instructions. Plus the original M68000 does not support moves from CCR. So in
|
|
// order to use CCR effectively one MUST use proper byte-size pseudo instructi-
|
|
// ons that will be resolved sometime after RA pass.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// --------------------------------------------------
|
|
/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
|
|
/// --------------------------------------------------
|
|
/// | EFFECTIVE ADDRESS
|
|
/// 0 1 0 0 0 1 0 0 1 1 | MODE | REG
|
|
/// --------------------------------------------------
|
|
let Defs = [CCR] in
|
|
class MxMoveToCCR<dag INS, MxEncEA EA, MxEncExt EXT>
|
|
: MxInst<(outs CCRC:$dst), INS, "move.w\t$src, $dst", [],
|
|
MxEncoding<EA.Reg, EA.DA, EA.Mode,
|
|
MxBead4Bits<0b0011>, MxBead4Bits<0b0001>, MxBead2Bits<0b01>,
|
|
EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>>;
|
|
|
|
class MxMoveToCCRPseudo<dag INS> : MxPseudo<(outs CCRC:$dst), INS>;
|
|
|
|
let mayLoad = 1 in {
|
|
def MOV16cp : MxMoveToCCR<(ins MxType16d.POp:$src), MxEncEAp_1, MxExtI16_1>;
|
|
def MOV8cp : MxMoveToCCRPseudo<(ins MxType8d.POp:$src)>;
|
|
} // let mayLoad = 1
|
|
|
|
def MOV16cd : MxMoveToCCR<(ins MxType16d.ROp:$src), MxEncEAd_1, MxExtEmpty>;
|
|
def MOV8cd : MxMoveToCCRPseudo<(ins MxType8d.ROp:$src)>;
|
|
|
|
/// Move from CCR
|
|
/// --------------------------------------------------
|
|
/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
|
|
/// --------------------------------------------------
|
|
/// | EFFECTIVE ADDRESS
|
|
/// 0 1 0 0 0 0 1 0 1 1 | MODE | REG
|
|
/// --------------------------------------------------
|
|
let Uses = [CCR] in
|
|
class MxMoveFromCCR<dag OUTS, dag INS, MxEncEA EA, MxEncExt EXT>
|
|
: MxInst<OUTS, INS, "move.w\t$src, $dst", [],
|
|
MxEncoding<EA.Reg, EA.DA, EA.Mode,
|
|
MxBead4Bits<0b1011>, MxBead4Bits<0b0000>, MxBead2Bits<0b01>,
|
|
EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>>,
|
|
Requires<[ IsM68010 ]>;
|
|
|
|
class MxMoveFromCCRPseudo<dag INS> : MxPseudo<(outs), INS>;
|
|
|
|
let mayStore = 1 in {
|
|
def MOV16pc
|
|
: MxMoveFromCCR<(outs), (ins MxType16d.POp:$dst, CCRC:$src), MxEncEAp_0, MxExtI16_0>;
|
|
def MOV8pc : MxMoveFromCCRPseudo<(ins MxType8d.POp:$dst, CCRC:$src)>;
|
|
} // let mayStore = 1
|
|
|
|
def MOV16dc
|
|
: MxMoveFromCCR<(outs MxType16d.ROp:$dst), (ins CCRC:$src), MxEncEAd_0, MxExtEmpty>;
|
|
|
|
def MOV8dc : MxMoveFromCCRPseudo<(ins MxType8d.ROp:$dst, CCRC:$src)>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// LEA
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ----------------------------------------------------
|
|
/// F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
|
|
/// ----------------------------------------------------
|
|
/// 0 1 0 0 | DST REG | 1 1 1 | MODE | REG
|
|
/// ----------------------------------------------------
|
|
class MxLEA<MxOperand SRCOpd, ComplexPattern SRCPat, MxEncEA EA, MxEncExt EXT>
|
|
: MxInst<(outs MxARD32:$dst), (ins SRCOpd:$src),
|
|
"lea\t$src, $dst", [(set i32:$dst, SRCPat:$src)],
|
|
MxEncoding<EA.Reg, EA.DA, EA.Mode,
|
|
MxBead3Bits<0b111>, MxBeadReg<0>, MxBead4Bits<0x4>,
|
|
EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>>;
|
|
|
|
def LEA32p : MxLEA<MxARID32, MxCP_ARID, MxEncEAp_1, MxExtI16_1>;
|
|
def LEA32f : MxLEA<MxARII32, MxCP_ARII, MxEncEAf_1, MxExtBrief_1>;
|
|
def LEA32q : MxLEA<MxPCD32, MxCP_PCD, MxEncEAq, MxExtI16_1>;
|
|
def LEA32b : MxLEA<MxAL32, MxCP_AL, MxEncEAb, MxExtI32_1>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudos
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Pushe/Pop to/from SP for simplicity
|
|
let Uses = [SP], Defs = [SP], hasSideEffects = 0 in {
|
|
|
|
// SP <- SP - <size>; (SP) <- Dn
|
|
let mayStore = 1 in {
|
|
def PUSH8d : MxPseudo<(outs), (ins DR8:$reg)>;
|
|
def PUSH16d : MxPseudo<(outs), (ins DR16:$reg)>;
|
|
def PUSH32r : MxPseudo<(outs), (ins XR32:$reg)>;
|
|
} // let mayStore = 1
|
|
|
|
// Dn <- (SP); SP <- SP + <size>
|
|
let mayLoad = 1 in {
|
|
def POP8d : MxPseudo<(outs DR8:$reg), (ins)>;
|
|
def POP16d : MxPseudo<(outs DR16:$reg), (ins)>;
|
|
def POP32r : MxPseudo<(outs XR32:$reg), (ins)>;
|
|
} // let mayLoad = 1
|
|
|
|
} // let Uses/Defs = [SP], hasSideEffects = 0
|
|
|
|
|
|
let Defs = [CCR] in {
|
|
class MxPseudoMove_RR<MxType DST, MxType SRC, list<dag> PAT = []>
|
|
: MxPseudo<(outs DST.ROp:$dst), (ins SRC.ROp:$src), PAT>;
|
|
|
|
class MxPseudoMove_RM<MxType DST, MxOperand SRCOpd, list<dag> PAT = []>
|
|
: MxPseudo<(outs DST.ROp:$dst), (ins SRCOpd:$src), PAT>;
|
|
}
|
|
|
|
/// This group of Pseudos is analogues to the real x86 extending moves, but
|
|
/// since M68k does not have those we need to emulate. These instructions
|
|
/// will be expanded right after RA completed because we need to know precisely
|
|
/// what registers are allocated for the operands and if they overlap we just
|
|
/// extend the value if the registers are completely different we need to move
|
|
/// first.
|
|
foreach EXT = ["S", "Z"] in {
|
|
let hasSideEffects = 0 in {
|
|
|
|
def MOV#EXT#Xd16d8 : MxPseudoMove_RR<MxType16d, MxType8d>;
|
|
def MOV#EXT#Xd32d8 : MxPseudoMove_RR<MxType32d, MxType8d>;
|
|
def MOV#EXT#Xd32d16 : MxPseudoMove_RR<MxType32r, MxType16r>;
|
|
|
|
let mayLoad = 1 in {
|
|
|
|
def MOV#EXT#Xd16j8 : MxPseudoMove_RM<MxType16d, MxType8.JOp>;
|
|
def MOV#EXT#Xd32j8 : MxPseudoMove_RM<MxType32d, MxType8.JOp>;
|
|
def MOV#EXT#Xd32j16 : MxPseudoMove_RM<MxType32d, MxType16.JOp>;
|
|
|
|
def MOV#EXT#Xd16p8 : MxPseudoMove_RM<MxType16d, MxType8.POp>;
|
|
def MOV#EXT#Xd32p8 : MxPseudoMove_RM<MxType32d, MxType8.POp>;
|
|
def MOV#EXT#Xd32p16 : MxPseudoMove_RM<MxType32d, MxType16.POp>;
|
|
|
|
def MOV#EXT#Xd16f8 : MxPseudoMove_RM<MxType16d, MxType8.FOp>;
|
|
def MOV#EXT#Xd32f8 : MxPseudoMove_RM<MxType32d, MxType8.FOp>;
|
|
def MOV#EXT#Xd32f16 : MxPseudoMove_RM<MxType32d, MxType16.FOp>;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
/// This group of instructions is similar to the group above but DOES NOT do
|
|
/// any value extension, they just load a smaller register into the lower part
|
|
/// of another register if operands' real registers are different or does
|
|
/// nothing if they are the same.
|
|
def MOVXd16d8 : MxPseudoMove_RR<MxType16d, MxType8d>;
|
|
def MOVXd32d8 : MxPseudoMove_RR<MxType32d, MxType8d>;
|
|
def MOVXd32d16 : MxPseudoMove_RR<MxType32r, MxType16r>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Extend/Truncate Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// i16 <- sext i8
|
|
def: Pat<(i16 (sext i8:$src)),
|
|
(EXTRACT_SUBREG (MOVSXd32d8 MxDRD8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxSExtLoadi16i8 MxCP_ARI:$src),
|
|
(EXTRACT_SUBREG (MOVSXd32j8 MxARI8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxSExtLoadi16i8 MxCP_ARID:$src),
|
|
(EXTRACT_SUBREG (MOVSXd32p8 MxARID8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxSExtLoadi16i8 MxCP_ARII:$src),
|
|
(EXTRACT_SUBREG (MOVSXd32f8 MxARII8:$src), MxSubRegIndex16Lo)>;
|
|
|
|
// i32 <- sext i8
|
|
def: Pat<(i32 (sext i8:$src)), (MOVSXd32d8 MxDRD8:$src)>;
|
|
def: Pat<(MxSExtLoadi32i8 MxCP_ARI :$src), (MOVSXd32j8 MxARI8 :$src)>;
|
|
def: Pat<(MxSExtLoadi32i8 MxCP_ARID:$src), (MOVSXd32p8 MxARID8:$src)>;
|
|
def: Pat<(MxSExtLoadi32i8 MxCP_ARII:$src), (MOVSXd32f8 MxARII8:$src)>;
|
|
|
|
// i32 <- sext i16
|
|
def: Pat<(i32 (sext i16:$src)), (MOVSXd32d16 MxDRD16:$src)>;
|
|
def: Pat<(MxSExtLoadi32i16 MxCP_ARI :$src), (MOVSXd32j16 MxARI16 :$src)>;
|
|
def: Pat<(MxSExtLoadi32i16 MxCP_ARID:$src), (MOVSXd32p16 MxARID16:$src)>;
|
|
def: Pat<(MxSExtLoadi32i16 MxCP_ARII:$src), (MOVSXd32f16 MxARII16:$src)>;
|
|
|
|
// i16 <- zext i8
|
|
def: Pat<(i16 (zext i8:$src)),
|
|
(EXTRACT_SUBREG (MOVZXd32d8 MxDRD8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxZExtLoadi16i8 MxCP_ARI:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32j8 MxARI8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxZExtLoadi16i8 MxCP_ARID:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32p8 MxARID8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxZExtLoadi16i8 MxCP_ARII:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32f8 MxARII8:$src), MxSubRegIndex16Lo)>;
|
|
|
|
// i32 <- zext i8
|
|
def: Pat<(i32 (zext i8:$src)), (MOVZXd32d8 MxDRD8:$src)>;
|
|
def: Pat<(MxZExtLoadi32i8 MxCP_ARI :$src), (MOVZXd32j8 MxARI8 :$src)>;
|
|
def: Pat<(MxZExtLoadi32i8 MxCP_ARID:$src), (MOVZXd32p8 MxARID8:$src)>;
|
|
def: Pat<(MxZExtLoadi32i8 MxCP_ARII:$src), (MOVZXd32f8 MxARII8:$src)>;
|
|
|
|
// i32 <- zext i16
|
|
def: Pat<(i32 (zext i16:$src)), (MOVZXd32d16 MxDRD16:$src)>;
|
|
def: Pat<(MxZExtLoadi32i16 MxCP_ARI :$src), (MOVZXd32j16 MxARI16 :$src)>;
|
|
def: Pat<(MxZExtLoadi32i16 MxCP_ARID:$src), (MOVZXd32p16 MxARID16:$src)>;
|
|
def: Pat<(MxZExtLoadi32i16 MxCP_ARII:$src), (MOVZXd32f16 MxARII16:$src)>;
|
|
|
|
// i16 <- anyext i8
|
|
def: Pat<(i16 (anyext i8:$src)),
|
|
(EXTRACT_SUBREG (MOVZXd32d8 MxDRD8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxExtLoadi16i8 MxCP_ARI:$src),
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(EXTRACT_SUBREG (MOVZXd32j8 MxARI8:$src), MxSubRegIndex16Lo)>;
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def: Pat<(MxExtLoadi16i8 MxCP_ARID:$src),
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(EXTRACT_SUBREG (MOVZXd32p8 MxARID8:$src), MxSubRegIndex16Lo)>;
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def: Pat<(MxExtLoadi16i8 MxCP_ARII:$src),
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(EXTRACT_SUBREG (MOVZXd32f8 MxARII8:$src), MxSubRegIndex16Lo)>;
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// i32 <- anyext i8
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def: Pat<(i32 (anyext i8:$src)), (MOVZXd32d8 MxDRD8:$src)>;
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def: Pat<(MxExtLoadi32i8 MxCP_ARI :$src), (MOVZXd32j8 MxARI8 :$src)>;
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def: Pat<(MxExtLoadi32i8 MxCP_ARID:$src), (MOVZXd32p8 MxARID8:$src)>;
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def: Pat<(MxExtLoadi32i8 MxCP_ARII:$src), (MOVZXd32f8 MxARII8:$src)>;
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// i32 <- anyext i16
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def: Pat<(i32 (anyext i16:$src)), (MOVZXd32d16 MxDRD16:$src)>;
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def: Pat<(MxExtLoadi32i16 MxCP_ARI :$src), (MOVZXd32j16 MxARI16 :$src)>;
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def: Pat<(MxExtLoadi32i16 MxCP_ARID:$src), (MOVZXd32p16 MxARID16:$src)>;
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def: Pat<(MxExtLoadi32i16 MxCP_ARII:$src), (MOVZXd32f16 MxARII16:$src)>;
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// trunc patterns
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def : Pat<(i16 (trunc i32:$src)),
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(EXTRACT_SUBREG MxXRD32:$src, MxSubRegIndex16Lo)>;
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def : Pat<(i8 (trunc i32:$src)),
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(EXTRACT_SUBREG MxXRD32:$src, MxSubRegIndex8Lo)>;
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def : Pat<(i8 (trunc i16:$src)),
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(EXTRACT_SUBREG MxXRD16:$src, MxSubRegIndex8Lo)>;
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