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51f907845b
Implement FoldImmediate for only integer aritihmetic operations. Add regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91150
122 lines
4.5 KiB
C++
122 lines
4.5 KiB
C++
//===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the VE implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H
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#define LLVM_LIB_TARGET_VE_VEINSTRINFO_H
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#include "VERegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "VEGenInstrInfo.inc"
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namespace llvm {
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class VESubtarget;
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/// VEII - This namespace holds all of the Aurora VE target-specific
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/// per-instruction flags. These must match the corresponding definitions in
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/// VEInstrFormats.td.
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namespace VEII {
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enum {
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// Aurora VE Instruction Flags. These flags describe the characteristics of
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// the Aurora VE instructions for vector handling.
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/// VE_Vector - This instruction is Vector Instruction.
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VE_Vector = 0x1,
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/// VE_VLInUse - This instruction has a vector register in its operands.
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VE_VLInUse = 0x2,
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/// VE_VLMask/Shift - This is a bitmask that selects the index number where
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/// an instruction holds vector length informatio (0 to 6, 7 means undef).n
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VE_VLShift = 2,
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VE_VLMask = 0x07 << VE_VLShift,
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};
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#define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse)
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#define GET_VLINDEX(TSF) \
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(HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1)
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} // end namespace VEII
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class VEInstrInfo : public VEGenInstrInfo {
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const VERegisterInfo RI;
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virtual void anchor();
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public:
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explicit VEInstrInfo(VESubtarget &ST);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const VERegisterInfo &getRegisterInfo() const { return RI; }
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/// Branch Analysis & Modification {
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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/// } Branch Analysis & Modification
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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/// Stack Spill & Reload {
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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/// } Stack Spill & Reload
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/// Optimization {
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
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MachineRegisterInfo *MRI) const override;
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/// } Optimization
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Register getGlobalBaseReg(MachineFunction *MF) const;
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// Lower pseudo instructions after register allocation.
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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bool expandExtendStackPseudo(MachineInstr &MI) const;
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bool expandGetStackTopPseudo(MachineInstr &MI) const;
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};
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} // namespace llvm
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#endif
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