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ff724f5a95
getARMVPTBlockMask was an outdated function that only handled basic
block masks: T, TT, TTT and TTTT. This worked fine before the MVE
VPT Block Insertion Pass improvements as it was the only kind of
masks that it could generate, but now it can generate more complex
masks that uses E predicates, so it's dangerous to use that function
to calculate VPT/VPST block masks.
I replaced it with 2 different functions:
- expandPredBlockMask, in ARMBaseInfo. This adds an "E" or "T" at
the end of an existing PredBlockMask.
- recomputeVPTBlockMask, in Thumb2InstrInfo. This takes an iterator
to a VPT/VPST instruction and recomputes its block mask by looking
at the predicated instructions that follows it. This should be
used to recompute a block mask after removing/adding a predicated
instruction to the block.
The expandPredBlockMask function is pretty much imported from the MVE
VPT Blocks pass.
I had to change the ARMLowOverheadLoops and MVEVPTBlocks passes as well
so they could use these new functions.
Differential Revision: https://reviews.llvm.org/D78201
238 lines
7.4 KiB
C++
238 lines
7.4 KiB
C++
//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the ARM target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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#define LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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namespace llvm {
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// Enums corresponding to ARM condition codes
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namespace ARMCC {
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// The CondCodes constants map directly to the 4-bit encoding of the
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// condition field for predicated instructions.
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enum CondCodes { // Meaning (integer) Meaning (floating-point)
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EQ, // Equal Equal
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NE, // Not equal Not equal, or unordered
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HS, // Carry set >, ==, or unordered
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LO, // Carry clear Less than
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MI, // Minus, negative Less than
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PL, // Plus, positive or zero >, ==, or unordered
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VS, // Overflow Unordered
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VC, // No overflow Not unordered
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HI, // Unsigned higher Greater than, or unordered
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LS, // Unsigned lower or same Less than or equal
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GE, // Greater than or equal Greater than or equal
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LT, // Less than Less than, or unordered
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GT, // Greater than Greater than
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LE, // Less than or equal <, ==, or unordered
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AL // Always (unconditional) Always (unconditional)
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};
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inline static CondCodes getOppositeCondition(CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return NE;
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case NE: return EQ;
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case HS: return LO;
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case LO: return HS;
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case MI: return PL;
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case PL: return MI;
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case VS: return VC;
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case VC: return VS;
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case HI: return LS;
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case LS: return HI;
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case GE: return LT;
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case LT: return GE;
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case GT: return LE;
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case LE: return GT;
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}
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}
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/// getSwappedCondition - assume the flags are set by MI(a,b), return
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/// the condition code if we modify the instructions such that flags are
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/// set by MI(b,a).
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inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
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switch (CC) {
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default: return ARMCC::AL;
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case ARMCC::EQ: return ARMCC::EQ;
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case ARMCC::NE: return ARMCC::NE;
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case ARMCC::HS: return ARMCC::LS;
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case ARMCC::LO: return ARMCC::HI;
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case ARMCC::HI: return ARMCC::LO;
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case ARMCC::LS: return ARMCC::HS;
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case ARMCC::GE: return ARMCC::LE;
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case ARMCC::LT: return ARMCC::GT;
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case ARMCC::GT: return ARMCC::LT;
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case ARMCC::LE: return ARMCC::GE;
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}
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}
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} // end namespace ARMCC
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namespace ARMVCC {
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enum VPTCodes {
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None = 0,
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Then,
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Else
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};
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} // namespace ARMVCC
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namespace ARM {
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/// Mask values for IT and VPT Blocks, to be used by MCOperands.
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/// Note that this is different from the "real" encoding used by the
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/// instructions. In this encoding, the lowest set bit indicates the end of
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/// the encoding, and above that, "1" indicates an else, while "0" indicates
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/// a then.
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/// Tx = x100
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/// Txy = xy10
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/// Txyz = xyz1
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enum class PredBlockMask {
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T = 0b1000,
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TT = 0b0100,
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TE = 0b1100,
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TTT = 0b0010,
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TTE = 0b0110,
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TEE = 0b1110,
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TET = 0b1010,
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TTTT = 0b0001,
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TTTE = 0b0011,
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TTEE = 0b0111,
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TTET = 0b0101,
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TEEE = 0b1111,
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TEET = 0b1101,
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TETT = 0b1001,
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TETE = 0b1011
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};
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} // namespace ARM
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// Expands a PredBlockMask by adding an E or a T at the end, depending on Kind.
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// e.g ExpandPredBlockMask(T, Then) = TT, ExpandPredBlockMask(TT, Else) = TTE,
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// and so on.
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ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask,
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ARMVCC::VPTCodes Kind);
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inline static const char *ARMVPTPredToString(ARMVCC::VPTCodes CC) {
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switch (CC) {
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case ARMVCC::None: return "none";
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case ARMVCC::Then: return "t";
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case ARMVCC::Else: return "e";
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}
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llvm_unreachable("Unknown VPT code");
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}
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inline static unsigned ARMVectorCondCodeFromString(StringRef CC) {
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return StringSwitch<unsigned>(CC.lower())
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.Case("t", ARMVCC::Then)
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.Case("e", ARMVCC::Else)
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.Default(~0U);
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}
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inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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switch (CC) {
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case ARMCC::EQ: return "eq";
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case ARMCC::NE: return "ne";
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case ARMCC::HS: return "hs";
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case ARMCC::LO: return "lo";
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case ARMCC::MI: return "mi";
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case ARMCC::PL: return "pl";
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case ARMCC::VS: return "vs";
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case ARMCC::VC: return "vc";
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case ARMCC::HI: return "hi";
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case ARMCC::LS: return "ls";
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case ARMCC::GE: return "ge";
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case ARMCC::LT: return "lt";
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case ARMCC::GT: return "gt";
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case ARMCC::LE: return "le";
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case ARMCC::AL: return "al";
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}
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llvm_unreachable("Unknown condition code");
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}
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inline static unsigned ARMCondCodeFromString(StringRef CC) {
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return StringSwitch<unsigned>(CC.lower())
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.Case("eq", ARMCC::EQ)
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.Case("ne", ARMCC::NE)
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.Case("hs", ARMCC::HS)
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.Case("cs", ARMCC::HS)
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.Case("lo", ARMCC::LO)
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.Case("cc", ARMCC::LO)
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.Case("mi", ARMCC::MI)
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.Case("pl", ARMCC::PL)
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.Case("vs", ARMCC::VS)
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.Case("vc", ARMCC::VC)
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.Case("hi", ARMCC::HI)
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.Case("ls", ARMCC::LS)
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.Case("ge", ARMCC::GE)
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.Case("lt", ARMCC::LT)
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.Case("gt", ARMCC::GT)
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.Case("le", ARMCC::LE)
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.Case("al", ARMCC::AL)
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.Default(~0U);
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}
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// System Registers
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namespace ARMSysReg {
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struct MClassSysReg {
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const char *Name;
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uint16_t M1Encoding12;
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uint16_t M2M3Encoding8;
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uint16_t Encoding;
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FeatureBitset FeaturesRequired;
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// return true if FeaturesRequired are all present in ActiveFeatures
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bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const {
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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// returns true if TestFeatures are all present in FeaturesRequired
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bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
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return (FeaturesRequired & TestFeatures) == TestFeatures;
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}
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};
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#define GET_MCLASSSYSREG_DECL
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#include "ARMGenSystemRegister.inc"
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// lookup system register using 12-bit SYSm value.
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// Note: the search is uniqued using M1 mask
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const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
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// returns APSR with _<bits> qualifier.
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// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
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const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
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// lookup system registers using 8-bit SYSm value
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const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
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} // end namespace ARMSysReg
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// Banked Registers
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namespace ARMBankedReg {
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struct BankedReg {
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const char *Name;
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uint16_t Encoding;
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};
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#define GET_BANKEDREG_DECL
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#include "ARMGenSystemRegister.inc"
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} // end namespace ARMBankedReg
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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