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66019b69d5
Recommitting after fixing AsmParser initialization and X86 inline asm error cleanup. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281762
111 lines
4.9 KiB
ArmAsm
111 lines
4.9 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
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// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
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.text
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//AdvSIMD RDMA vector
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sqrdmlah v0.4h, v1.4h, v2.4h
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sqrdmlsh v0.4h, v1.4h, v2.4h
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sqrdmlah v0.2s, v1.2s, v2.2s
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sqrdmlsh v0.2s, v1.2s, v2.2s
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sqrdmlah v0.4s, v1.4s, v2.4s
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sqrdmlsh v0.4s, v1.4s, v2.4s
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sqrdmlah v0.8h, v1.8h, v2.8h
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sqrdmlsh v0.8h, v1.8h, v2.8h
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// CHECK: sqrdmlah v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x42,0x2e]
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// CHECK: sqrdmlsh v0.4h, v1.4h, v2.4h // encoding: [0x20,0x8c,0x42,0x2e]
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// CHECK: sqrdmlah v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0x82,0x2e]
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// CHECK: sqrdmlsh v0.2s, v1.2s, v2.2s // encoding: [0x20,0x8c,0x82,0x2e]
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// CHECK: sqrdmlah v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0x82,0x6e]
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// CHECK: sqrdmlsh v0.4s, v1.4s, v2.4s // encoding: [0x20,0x8c,0x82,0x6e]
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// CHECK: sqrdmlah v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x42,0x6e]
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// CHECK: sqrdmlsh v0.8h, v1.8h, v2.8h // encoding: [0x20,0x8c,0x42,0x6e]
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sqrdmlah v0.2h, v1.2h, v2.2h
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// CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
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sqrdmlsh v0.2h, v1.2h, v2.2h
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// CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
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sqrdmlah v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
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// CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
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// CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
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sqrdmlsh v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
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// CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
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// CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
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sqrdmlah v0.2s, v1.4h, v2.8h
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// CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
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sqrdmlsh v0.4s, v1.8h, v2.2s
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// CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
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//AdvSIMD RDMA scalar
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sqrdmlah h0, h1, h2
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sqrdmlsh h0, h1, h2
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sqrdmlah s0, s1, s2
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sqrdmlsh s0, s1, s2
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// CHECK: sqrdmlah h0, h1, h2 // encoding: [0x20,0x84,0x42,0x7e]
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// CHECK: sqrdmlsh h0, h1, h2 // encoding: [0x20,0x8c,0x42,0x7e]
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// CHECK: sqrdmlah s0, s1, s2 // encoding: [0x20,0x84,0x82,0x7e]
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// CHECK: sqrdmlsh s0, s1, s2 // encoding: [0x20,0x8c,0x82,0x7e]
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//AdvSIMD RDMA vector by-element
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sqrdmlah v0.4h, v1.4h, v2.h[3]
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sqrdmlsh v0.4h, v1.4h, v2.h[3]
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sqrdmlah v0.2s, v1.2s, v2.s[1]
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sqrdmlsh v0.2s, v1.2s, v2.s[1]
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sqrdmlah v0.8h, v1.8h, v2.h[3]
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sqrdmlsh v0.8h, v1.8h, v2.h[3]
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sqrdmlah v0.4s, v1.4s, v2.s[3]
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sqrdmlsh v0.4s, v1.4s, v2.s[3]
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// CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3] // encoding: [0x20,0xd0,0x72,0x2f]
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// CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3] // encoding: [0x20,0xf0,0x72,0x2f]
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// CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1] // encoding: [0x20,0xd0,0xa2,0x2f]
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// CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1] // encoding: [0x20,0xf0,0xa2,0x2f]
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// CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3] // encoding: [0x20,0xd0,0x72,0x6f]
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// CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3] // encoding: [0x20,0xf0,0x72,0x6f]
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// CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3] // encoding: [0x20,0xd8,0xa2,0x6f]
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// CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3] // encoding: [0x20,0xf8,0xa2,0x6f]
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sqrdmlah v0.4s, v1.2s, v2.s[1]
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sqrdmlsh v0.2s, v1.2d, v2.s[1]
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sqrdmlah v0.8h, v1.8h, v2.s[3]
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sqrdmlsh v0.8h, v1.8h, v2.h[8]
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah v0.4s, v1.2s, v2.s[1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlsh v0.2s, v1.2d, v2.s[1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah v0.8h, v1.8h, v2.s[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: vector lane must be an integer in range [0, 7].
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// CHECK-ERROR: sqrdmlsh v0.8h, v1.8h, v2.h[8]
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// CHECK-ERROR: ^
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//AdvSIMD RDMA scalar by-element
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sqrdmlah h0, h1, v2.h[3]
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sqrdmlsh h0, h1, v2.h[3]
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sqrdmlah s0, s1, v2.s[3]
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sqrdmlsh s0, s1, v2.s[3]
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// CHECK: sqrdmlah h0, h1, v2.h[3] // encoding: [0x20,0xd0,0x72,0x7f]
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// CHECK: sqrdmlsh h0, h1, v2.h[3] // encoding: [0x20,0xf0,0x72,0x7f]
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// CHECK: sqrdmlah s0, s1, v2.s[3] // encoding: [0x20,0xd8,0xa2,0x7f]
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// CHECK: sqrdmlsh s0, s1, v2.s[3] // encoding: [0x20,0xf8,0xa2,0x7f]
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sqrdmlah b0, h1, v2.h[3]
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sqrdmlah s0, d1, v2.s[3]
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sqrdmlsh h0, h1, v2.s[3]
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sqrdmlsh s0, s1, v2.s[4]
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah b0, h1, v2.h[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah s0, d1, v2.s[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlsh h0, h1, v2.s[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: vector lane must be an integer in range [0, 3].
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// CHECK-ERROR: sqrdmlsh s0, s1, v2.s[4]
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// CHECK-ERROR: ^
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