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30264d4391
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
129 lines
3.7 KiB
LLVM
129 lines
3.7 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i64 0, align 8
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define signext i32 @test_igesll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r3, 63
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; CHECK-NEXT: rldicl r6, r4, 1, 63
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; CHECK-NEXT: subfc r3, r4, r3
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r3, 63
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; CHECK-NEXT: rldicl r6, r4, 1, 63
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; CHECK-NEXT: subfc r3, r4, r3
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_igesll_z(i64 %a) {
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; CHECK-LABEL: test_igesll_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_igesll_sext_z(i64 %a) {
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; CHECK-LABEL: test_igesll_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: not r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_igesll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: sradi r6, r3, 63
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; CHECK: subfc r3, r4, r3
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; CHECK: rldicl r3, r4, 1, 63
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; CHECK: adde r3, r6, r3
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; CHECK: std r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_igesll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r6, r3, 63
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: subfc r3, r4, r3
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; CHECK-NEXT: rldicl r3, r4, 1, 63
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: adde r3, r6, r3
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_igesll_z_store(i64 %a) {
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; CHECK-LABEL: test_igesll_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_igesll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_igesll_sext_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: not r3, r3
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; CHECK-NEXT: std r3,
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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