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AsmParser
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AMDGPU: Consolidate inline immediate predicate functions
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2016-12-05 22:26:17 +00:00 |
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Disassembler
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AMDGPU: Disallow exec as SMEM instruction operand
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2016-11-29 19:39:53 +00:00 |
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InstPrinter
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AMDGPU: Change how exp is printed
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2016-12-05 20:31:49 +00:00 |
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MCTargetDesc
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
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2016-11-19 13:05:44 +00:00 |
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TargetInfo
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Move the global variables representing each Target behind accessor function
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2016-10-09 23:00:34 +00:00 |
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Utils
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AMDGPU: Consolidate inline immediate predicate functions
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2016-12-05 22:26:17 +00:00 |
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AMDGPU.h
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[AMDGPU] Add amdgpu-unify-metadata pass
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2016-12-08 19:46:04 +00:00 |
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AMDGPU.td
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[AMDGPU] Add f16 support (VI+)
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2016-11-13 07:01:11 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPUAnnotateUniformValues.cpp
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[AMDGPU] Scalarization of global uniform loads.
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2016-12-08 17:28:47 +00:00 |
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AMDGPUAsmPrinter.cpp
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AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objects
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2016-12-09 19:49:48 +00:00 |
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AMDGPUAsmPrinter.h
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AMDGPU: Emit runtime metadata as a note element in .note section
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2016-11-10 21:18:49 +00:00 |
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AMDGPUCallingConv.td
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AMDGPUCallLowering.cpp
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AMDGPUCallLowering.h
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AMDGPUCodeGenPrepare.cpp
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AMDGPU: Fix crash on i16 constant expression
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2016-12-06 23:18:06 +00:00 |
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
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MachineScheduler: Export function to construct "default" scheduler.
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2016-11-28 20:11:54 +00:00 |
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AMDGPUInstrInfo.h
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MachineScheduler: Export function to construct "default" scheduler.
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2016-11-28 20:11:54 +00:00 |
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AMDGPUInstrInfo.td
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AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.
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2016-12-07 02:42:15 +00:00 |
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AMDGPUInstructions.td
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[AMDGPU] Add f16 support (VI+)
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2016-11-13 07:01:11 +00:00 |
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AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
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AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.
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2016-12-07 02:42:15 +00:00 |
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AMDGPUISelLowering.cpp
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AMDGPU: Fix i128 mul
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2016-12-09 17:49:14 +00:00 |
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AMDGPUISelLowering.h
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AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.
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2016-12-07 02:42:15 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPU/SI: Set correct value for amd_kernel_code_t::kernarg_segment_alignment
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2016-12-06 21:53:10 +00:00 |
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AMDGPUMCInstLower.cpp
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[AMDGPU] Add wave barrier builtin
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2016-11-15 19:00:15 +00:00 |
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AMDGPUMCInstLower.h
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AMDGPUOpenCLImageTypeLoweringPass.cpp
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AMDGPUPromoteAlloca.cpp
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AMDGPUPTNote.h
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AMDGPU: Emit runtime metadata as a note element in .note section
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2016-11-10 21:18:49 +00:00 |
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPURuntimeMetadata.h
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AMDGPU: Attempt to fix build failure on x86-64 selfhost build
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2016-11-11 02:48:50 +00:00 |
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AMDGPUSubtarget.cpp
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[AMDGPU] Scalarization of global uniform loads.
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2016-12-08 17:28:47 +00:00 |
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AMDGPUSubtarget.h
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[AMDGPU] Scalarization of global uniform loads.
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2016-12-08 17:28:47 +00:00 |
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AMDGPUTargetMachine.cpp
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[AMDGPU] Add amdgpu-unify-metadata pass
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2016-12-08 19:46:04 +00:00 |
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AMDGPUTargetMachine.h
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[AMDGPU] Add amdgpu-unify-metadata pass
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2016-12-08 19:46:04 +00:00 |
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AMDGPUTargetObjectFile.cpp
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Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject.
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2016-10-24 19:23:39 +00:00 |
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AMDGPUTargetObjectFile.h
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Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject.
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2016-10-24 19:23:39 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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AMDGPUTargetTransformInfo.h
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Do a sweep over move ctors and remove those that are identical to the default.
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2016-10-20 12:20:28 +00:00 |
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AMDGPUUnifyMetadata.cpp
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[AMDGPU] Add amdgpu-unify-metadata pass
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2016-12-08 19:46:04 +00:00 |
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AMDILCFGStructurizer.cpp
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AMDKernelCodeT.h
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BUFInstructions.td
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AMDGPU: Add VI i16 support
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2016-11-10 16:02:37 +00:00 |
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CaymanInstructions.td
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CIInstructions.td
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CMakeLists.txt
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[AMDGPU] Add amdgpu-unify-metadata pass
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2016-12-08 19:46:04 +00:00 |
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DSInstructions.td
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AMDGPU: Add VI i16 support
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2016-11-10 16:02:37 +00:00 |
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EvergreenInstructions.td
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FLATInstructions.td
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AMDGPU: Rename flat operands to match mubuf
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2016-11-29 19:30:44 +00:00 |
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GCNHazardRecognizer.cpp
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AMDGPU: Rename flat operands to match mubuf
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2016-11-29 19:30:44 +00:00 |
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GCNHazardRecognizer.h
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AMDGPU/SI: Handle hazard with s_rfe_b64
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2016-10-27 23:50:21 +00:00 |
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GCNSchedStrategy.cpp
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AMDGPU/SI: Allow using SGPRs 96-101 on VI
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2016-12-09 19:49:40 +00:00 |
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GCNSchedStrategy.h
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LLVMBuild.txt
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MIMGInstructions.td
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[AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>
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2016-11-15 13:39:07 +00:00 |
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Processors.td
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AMDGPU: Refactor processor definition to use ISA version features
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2016-10-26 16:37:56 +00:00 |
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600FrameLowering.h
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R600InstrFormats.td
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R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
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AMDGPU: Refactor exp instructions
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2016-12-05 20:23:10 +00:00 |
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R600Intrinsics.td
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R600ISelLowering.cpp
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AMDGPU: Refactor exp instructions
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2016-12-05 20:23:10 +00:00 |
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R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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Fix spelling mistakes in AMDGPU target comments. NFC.
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2016-11-18 11:04:02 +00:00 |
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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SIDebuggerInsertNops.cpp
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SIDefines.h
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AMDGPU: Clean up instruction bits
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2016-12-09 17:49:08 +00:00 |
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SIFixControlFlowLiveIntervals.cpp
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SIFixSGPRCopies.cpp
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AMDGPU/SI: Don't move copies of immediates to the VALU
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2016-12-06 21:13:30 +00:00 |
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SIFoldOperands.cpp
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AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.
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2016-12-07 02:42:15 +00:00 |
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SIFrameLowering.cpp
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AMDGPU: Fix using incorrect private resource with no allocation
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2016-10-28 19:43:31 +00:00 |
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SIFrameLowering.h
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SIInsertSkips.cpp
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AMDGPU: Refactor exp instructions
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2016-12-05 20:23:10 +00:00 |
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SIInsertWaits.cpp
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AMDGPU: Refactor exp instructions
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2016-12-05 20:23:10 +00:00 |
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SIInstrFormats.td
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AMDGPU: Clean up instruction bits
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2016-12-09 17:49:08 +00:00 |
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SIInstrInfo.cpp
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AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.
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2016-12-07 02:42:15 +00:00 |
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SIInstrInfo.h
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AMDGPU: Refactor exp instructions
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2016-12-05 20:23:10 +00:00 |
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SIInstrInfo.td
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AMDGPU: Assembler support for exp
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2016-12-05 20:42:41 +00:00 |
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SIInstructions.td
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AMDGPU: Make f16 ConstantFP legal
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2016-12-08 20:14:46 +00:00 |
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SIIntrinsics.td
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AMDGPU: Refactor exp instructions
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2016-12-05 20:23:10 +00:00 |
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SIISelLowering.cpp
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AMDGPU: Fix isTypeDesirableForOp for i16
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2016-12-09 17:57:43 +00:00 |
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SIISelLowering.h
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AMDGPU: Make f16 ConstantFP legal
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2016-12-08 20:14:46 +00:00 |
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SILoadStoreOptimizer.cpp
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[AMDGPU][CodeGen] To improve CGEMM performance: combine LDS reads.
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2016-11-03 14:37:13 +00:00 |
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SILowerControlFlow.cpp
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[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies
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2016-11-28 18:58:49 +00:00 |
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SILowerI1Copies.cpp
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[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies
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2016-11-28 18:58:49 +00:00 |
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIMachineScheduler.cpp
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Fix spelling mistakes in AMDGPU target comments. NFC.
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2016-11-18 11:04:02 +00:00 |
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SIMachineScheduler.h
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SIOptimizeExecMasking.cpp
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SIRegisterInfo.cpp
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AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objects
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2016-12-09 19:49:48 +00:00 |
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SIRegisterInfo.h
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AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objects
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2016-12-09 19:49:48 +00:00 |
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SIRegisterInfo.td
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AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions
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2016-12-09 17:49:11 +00:00 |
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SISchedule.td
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SIShrinkInstructions.cpp
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[AMDGPU] Add f16 support (VI+)
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2016-11-13 07:01:11 +00:00 |
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SITypeRewriter.cpp
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SIWholeQuadMode.cpp
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AMDGPU/SI: Add back reverted SGPR spilling code, but disable it
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2016-11-25 17:37:09 +00:00 |
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SMInstructions.td
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[AMDGPU] Scalarization of global uniform loads.
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2016-12-08 17:28:47 +00:00 |
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SOPInstructions.td
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AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.
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2016-12-07 02:42:15 +00:00 |
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VIInstrFormats.td
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VIInstructions.td
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AMDGPU: Add VI i16 support
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2016-11-10 16:02:37 +00:00 |
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VOP1Instructions.td
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
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2016-11-19 13:05:44 +00:00 |
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VOP2Instructions.td
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AMDGPU: Select i16 instructions to VOP3 forms
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2016-12-09 06:19:12 +00:00 |
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VOP3Instructions.td
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[AMDGPU] Handle f16 select{_cc}
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2016-11-16 03:16:26 +00:00 |
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VOPCInstructions.td
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[AMDGPU] Add f16 support (VI+)
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2016-11-13 07:01:11 +00:00 |
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VOPInstructions.td
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Fix spelling mistakes in AMDGPU target comments. NFC.
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2016-11-18 11:04:02 +00:00 |
