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8ec20feca4
This improves AA in the MI schduler when reason about paired instructions. Phabricator Revision: http://reviews.llvm.org/D17098 PR26358 llvm-svn: 266462
22 lines
882 B
LLVM
22 lines
882 B
LLVM
; RUN: llc < %s -mtriple=arm64-apple-darwin -enable-misched=false -enable-post-misched=false | FileCheck %s
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; rdar://12713765
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; Make sure we are not creating stack objects that are assumed to be 64-byte
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; aligned.
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@T3_retval = common global <16 x float> zeroinitializer, align 16
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define void @test(<16 x float>* noalias sret %agg.result) nounwind ssp {
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entry:
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; CHECK: test
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; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32]
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; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp]
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; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32]
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; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>, <16 x float>* @T3_retval, align 16
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store <16 x float> %0, <16 x float>* %retval
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%1 = load <16 x float>, <16 x float>* %retval
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store <16 x float> %1, <16 x float>* %agg.result, align 16
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ret void
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}
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