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The ABI allows sub-128 vectors to be passed and returned in registers, with the vector occupying the upper part of a register. We therefore want to legalize those types by widening the vector rather than promoting the elements. The patch includes some simple tests for sub-128 vectors and also tests that we can recognize various pack sequences, some of which use sub-128 vectors as temporary results. One of these forms is based on the pack sequences generated by llvmpipe when no intrinsics are used. Signed unpacks are recognized as BUILD_VECTORs whose elements are individually sign-extended. Unsigned unpacks can have the equivalent form with zero extension, but they also occur as shuffles in which some elements are zero. Based on a patch by Richard Sandiford. llvm-svn: 236525
108 lines
2.2 KiB
LLVM
108 lines
2.2 KiB
LLVM
; Test vector register moves.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v16i8 moves.
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define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <16 x i8> %val2
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}
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; Test v8i16 moves.
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define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <8 x i16> %val2
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}
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; Test v4i32 moves.
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define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <4 x i32> %val2
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}
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; Test v2i64 moves.
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define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <2 x i64> %val2
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}
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; Test v4f32 moves.
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define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <4 x float> %val2
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}
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; Test v2f64 moves.
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define <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <2 x double> %val2
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}
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; Test v2i8 moves.
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define <2 x i8> @f7(<2 x i8> %val1, <2 x i8> %val2) {
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; CHECK-LABEL: f7:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <2 x i8> %val2
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}
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; Test v4i8 moves.
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define <4 x i8> @f8(<4 x i8> %val1, <4 x i8> %val2) {
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; CHECK-LABEL: f8:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <4 x i8> %val2
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}
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; Test v8i8 moves.
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define <8 x i8> @f9(<8 x i8> %val1, <8 x i8> %val2) {
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; CHECK-LABEL: f9:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <8 x i8> %val2
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}
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; Test v2i16 moves.
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define <2 x i16> @f10(<2 x i16> %val1, <2 x i16> %val2) {
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; CHECK-LABEL: f10:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <2 x i16> %val2
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}
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; Test v4i16 moves.
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define <4 x i16> @f11(<4 x i16> %val1, <4 x i16> %val2) {
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; CHECK-LABEL: f11:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <4 x i16> %val2
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}
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; Test v2i32 moves.
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define <2 x i32> @f12(<2 x i32> %val1, <2 x i32> %val2) {
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; CHECK-LABEL: f12:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <2 x i32> %val2
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}
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; Test v2f32 moves.
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define <2 x float> @f13(<2 x float> %val1, <2 x float> %val2) {
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; CHECK-LABEL: f13:
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; CHECK: vlr %v24, %v26
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; CHECK: br %r14
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ret <2 x float> %val2
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}
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