Thomas Lively bb4e957ebf [WebAssembly] Codegen for extmul SIMD instructions ... Replace the clang builtins and LLVM intrinsics for the SIMD extmul instructions with normal codegen patterns. Differential Revision: https://reviews.llvm.org/D106724		2021-07-27 08:41:30 -07:00
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Analysis	[Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation	2021-07-26 17:15:43 +01:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[WebAssembly] Codegen for extmul SIMD instructions	2021-07-27 08:41:30 -07:00
DebugInfo	[DebugInfo][InstrRef] Handle llvm.frameaddress intrinsics gracefully	2021-07-27 13:44:37 +01:00
Demangle
Examples
ExecutionEngine	[JITLink][RISCV] Run new test from 0ad562b48 only if the RISCV backend is enabled	2021-07-25 10:47:26 -04:00
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker
LTO
MachineVerifier
MC	[AArch64][SME] Add zero instruction	2021-07-27 08:35:45 +00:00
Object	[llvm-readobj] Display multiple function names for stack size entries	2021-07-26 14:49:53 +01:00
ObjectYAML	[yaml2obj][MachO] Rename PayloadString to Content	2021-07-26 09:04:51 -07:00
Other	[ConstantFold] Fix GEP of GEP fold with opaque pointers	2021-07-23 23:56:41 +02:00
SafepointIRVerifier
Support
SymbolRewriter
TableGen
ThinLTO/X86
tools	[Debug-Info][llvm-dwarfdump] Don't try to dump location	2021-07-27 07:28:59 +00:00
Transforms	Strip undef implying attributes when moving calls	2021-07-27 10:57:05 -04:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh