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a515fb7c17
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
35 lines
1.1 KiB
LLVM
35 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @build_vector2
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK-NOT: MOV
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; SI-CHECK: @build_vector2
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; SI-CHECK-DAG: V_MOV_B32_e32 [[X:VGPR[0-9]]], 5
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; SI-CHECK-DAG: V_MOV_B32_e32 [[Y:VGPR[0-9]]], 6
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; SI-CHECK: BUFFER_STORE_DWORDX2 [[X]]_[[Y]]
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define void @build_vector2 (<2 x i32> addrspace(1)* %out) {
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entry:
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store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @build_vector4
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK: MOV
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; R600-CHECK-NOT: MOV
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; SI-CHECK: @build_vector4
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; SI-CHECK-DAG: V_MOV_B32_e32 [[X:VGPR[0-9]]], 5
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; SI-CHECK-DAG: V_MOV_B32_e32 [[Y:VGPR[0-9]]], 6
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; SI-CHECK-DAG: V_MOV_B32_e32 [[Z:VGPR[0-9]]], 7
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; SI-CHECK-DAG: V_MOV_B32_e32 [[W:VGPR[0-9]]], 8
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; SI-CHECK: BUFFER_STORE_DWORDX4 [[X]]_[[Y]]_[[Z]]_[[W]]
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define void @build_vector4 (<4 x i32> addrspace(1)* %out) {
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entry:
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store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
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ret void
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}
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