1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 11:02:59 +02:00
llvm-mirror/include/llvm/Target
Amara Emerson bbd25a9a88 [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions.
These mirror the IR and SelectionDAG intrinsics & nodes.

Opcodes added:
G_VECREDUCE_SEQ_FADD
G_VECREDUCE_SEQ_FMUL
G_VECREDUCE_FADD
G_VECREDUCE_FMUL
G_VECREDUCE_FMAX
G_VECREDUCE_FMIN
G_VECREDUCE_ADD
G_VECREDUCE_MUL
G_VECREDUCE_AND
G_VECREDUCE_OR
G_VECREDUCE_XOR
G_VECREDUCE_SMAX
G_VECREDUCE_SMIN
G_VECREDUCE_UMAX
G_VECREDUCE_UMIN

Differential Revision: https://reviews.llvm.org/D88750
2020-10-08 10:33:19 -07:00
..
GlobalISel [GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y) 2020-09-28 10:08:14 -07:00
CodeGenCWrappers.h
GenericOpcodes.td [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions. 2020-10-08 10:33:19 -07:00
Target.td [DebugInstrRef][1/9] Add fields for instr-ref variable locations 2020-09-14 10:06:52 +01:00
TargetCallingConv.td Reland [X86] Codegen for preallocated 2020-05-20 11:25:44 -07:00
TargetInstrPredicate.td
TargetIntrinsicInfo.h TargetIntrinsicInfo.h - remove unnecessary Compiler.h include. NFC. 2020-05-19 09:28:13 +01:00
TargetItinerary.td [llvm] NFC: Fix trivial typo in rst and td files 2020-04-23 14:26:32 +09:00
TargetLoweringObjectFile.h Revert "Reland [CodeGen] emit CG profile for COFF object file" 2020-09-27 22:43:14 -07:00
TargetMachine.h [AIX] add new option -mignore-xcoff-visibility 2020-10-08 09:34:58 -04:00
TargetOptions.h [AIX] add new option -mignore-xcoff-visibility 2020-10-08 09:34:58 -04:00
TargetPfmCounters.td
TargetSchedule.td [llvm] NFC: Fix trivial typo in rst and td files 2020-04-23 14:26:32 +09:00
TargetSelectionDAG.td [Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics. 2020-08-07 15:09:24 +02:00