mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
bbf5be9d55
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
268 lines
12 KiB
YAML
268 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=t2-reduce-size %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8m.main"
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%list_head = type { %list_head*, %list_data* }
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%list_data = type { i16, i16 }
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define %list_head* @reg_reg_it_block(%list_head* %a, i16 zeroext %b) {
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entry:
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br label %while.begin
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while.begin: ; preds = %while.body.end, %entry
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%list.addr.i = phi %list_head* [ %ld.5, %while.body.end ], [ %a, %entry ]
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%info.i = getelementptr inbounds %list_head, %list_head* %list.addr.i, i32 0, i32 1
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%ld.0 = load %list_data*, %list_data** %info.i, align 4
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%data16.i1 = bitcast %list_data* %ld.0 to i16*
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%ld.1 = load i16, i16* %data16.i1, align 2
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%xor.1 = xor i16 %ld.1, %b
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%cmp.i = icmp eq i16 %xor.1, 0
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br i1 %cmp.i, label %exit, label %while.body.a
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while.body.a: ; preds = %while.begin
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%next.i2 = bitcast %list_head* %list.addr.i to %list_head**
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%ld.2 = load %list_head*, %list_head** %next.i2, align 4
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%cmp.i.1 = icmp eq %list_head* %ld.2, null
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br i1 %cmp.i.1, label %exit, label %it.block
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it.block: ; preds = %while.body.a
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%info.i.1 = getelementptr inbounds %list_head, %list_head* %ld.2, i32 0, i32 1
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%ld.3 = load %list_data*, %list_data** %info.i.1, align 4
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%data16.i.13 = bitcast %list_data* %ld.3 to i16*
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%ld.4 = load i16, i16* %data16.i.13, align 2
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%xor.2 = xor i16 %ld.4, %b
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%cmp.i.2 = icmp eq i16 %xor.2, 0
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br i1 %cmp.i.2, label %exit, label %while.body.end
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while.body.end: ; preds = %it.block
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%next.i.14 = bitcast %list_head* %ld.2 to %list_head**
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%ld.5 = load %list_head*, %list_head** %next.i.14, align 4
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%cmp.i.3 = icmp eq %list_head* %ld.5, null
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br i1 %cmp.i.3, label %exit, label %while.begin
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exit: ; preds = %while.body.end, %it.block, %while.body.a, %while.begin
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%res = phi %list_head* [ %list.addr.i, %while.begin ], [ %ld.2, %while.body.a ], [ %ld.2, %it.block ], [ %ld.5, %while.body.end ]
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ret %list_head* %res
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}
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define i16 @op_not_killed(%list_head* %a, i16 zeroext %b) {
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entry:
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br label %while.begin
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while.begin: ; preds = %while.body.end, %entry
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%list.addr.i = phi %list_head* [ %ld.5, %while.body.end ], [ %a, %entry ]
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%info.i = getelementptr inbounds %list_head, %list_head* %list.addr.i, i32 0, i32 1
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%ld.0 = load %list_data*, %list_data** %info.i, align 4
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%data16.i1 = bitcast %list_data* %ld.0 to i16*
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%ld.1 = load i16, i16* %data16.i1, align 2
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%xor.1 = xor i16 %ld.1, %b
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%cmp.i = icmp eq i16 %xor.1, 0
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br i1 %cmp.i, label %exit, label %while.body.a
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while.body.a: ; preds = %while.begin
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%next.i2 = bitcast %list_head* %list.addr.i to %list_head**
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%ld.2 = load %list_head*, %list_head** %next.i2, align 4
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%cmp.i.1 = icmp eq %list_head* %ld.2, null
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br i1 %cmp.i.1, label %exit, label %it.block
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it.block: ; preds = %while.body.a
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%info.i.1 = getelementptr inbounds %list_head, %list_head* %ld.2, i32 0, i32 1
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%ld.3 = load %list_data*, %list_data** %info.i.1, align 4
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%data16.i.13 = bitcast %list_data* %ld.3 to i16*
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%ld.4 = load i16, i16* %data16.i.13, align 2
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%xor.2 = xor i16 %ld.4, %b
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%cmp.i.2 = icmp eq i16 %xor.2, 0
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br i1 %cmp.i.2, label %exit, label %while.body.end
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while.body.end: ; preds = %it.block
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%next.i.14 = bitcast %list_head* %ld.2 to %list_head**
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%ld.5 = load %list_head*, %list_head** %next.i.14, align 4
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%cmp.i.3 = icmp eq %list_head* %ld.5, null
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br i1 %cmp.i.3, label %exit, label %while.begin
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exit: ; preds = %while.body.end, %it.block, %while.body.a, %while.begin
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%res = phi i16 [ %ld.1, %while.begin ], [ %ld.1, %while.body.a ], [ %ld.4, %it.block ], [ %ld.4, %while.body.end ]
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ret i16 %res
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}
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...
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---
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name: reg_reg_it_block
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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body: |
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; CHECK-LABEL: name: reg_reg_it_block
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
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; CHECK: bb.1.while.body.end:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i.14)
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; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: BUNDLE implicit-def dead $itstate, implicit killed $cpsr, implicit $r0 {
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit internal killed $itstate
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; CHECK: }
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; CHECK: bb.2.while.begin:
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; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info.i)
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; CHECK: renamable $r2 = tLDRHi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16.i1)
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; CHECK: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg
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; CHECK: t2Bcc %bb.4, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.3.while.body.a:
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; CHECK: successors: %bb.4(0x4207fef8), %bb.1(0x3df80108)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i2)
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; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: BUNDLE implicit-def dead $itstate, implicit-def dead $r2, implicit-def $cpsr, implicit $r0, implicit killed $cpsr, implicit $r1 {
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; CHECK: t2IT 1, 30, implicit-def $itstate
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; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 1 /* CC::ne */, $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1)
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; CHECK: renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1 /* CC::ne */, $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13)
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; CHECK: t2TEQrr internal killed renamable $r2, renamable $r1, 1 /* CC::ne */, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
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; CHECK: }
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; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
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; CHECK: bb.4.exit:
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; CHECK: liveins: $r0
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1
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t2B %bb.1, 14, $noreg
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bb.3.while.body.end:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1
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renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i.14)
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tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
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BUNDLE implicit-def dead $itstate, implicit killed $cpsr, implicit $r0 {
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t2IT 0, 8, implicit-def $itstate
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tBX_RET 0, killed $cpsr, implicit $r0, implicit internal killed $itstate
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}
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bb.1.while.begin:
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successors: %bb.4(0x04000000), %bb.2(0x7c000000)
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liveins: $r0, $r1
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renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info.i)
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renamable $r2 = tLDRHi killed renamable $r2, 0, 14, $noreg :: (load 2 from %ir.data16.i1)
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dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
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t2Bcc %bb.4, 0, killed $cpsr
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bb.2.while.body.a:
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successors: %bb.4(0x80000000), %bb.3(0x78200000)
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liveins: $r0, $r1
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renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i2)
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tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
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BUNDLE implicit-def dead $itstate, implicit-def dead $r2, implicit-def $cpsr, implicit $r0, implicit killed $cpsr, implicit $r1 {
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t2IT 1, 30, implicit-def $itstate
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renamable $r2 = tLDRi renamable $r0, 1, 1, $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1)
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renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1, $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13)
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t2TEQrr internal killed renamable $r2, renamable $r1, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
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}
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t2Bcc %bb.3, 1, killed $cpsr
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bb.4.exit:
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liveins: $r0
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tBX_RET 14, $noreg, implicit killed $r0
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...
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---
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name: op_not_killed
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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body: |
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; CHECK-LABEL: name: op_not_killed
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
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; CHECK: bb.1.while.begin:
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; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
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; CHECK: liveins: $r1, $r2
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; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info.i)
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; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16.i1)
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; CHECK: t2TEQrr renamable $r0, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.2.while.body.a:
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; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i2)
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; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.3.it.block:
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; CHECK: successors: %bb.5(0x04000000), %bb.4(0x7c000000)
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; CHECK: liveins: $r1, $r2
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; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info.i.1)
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; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16.i.13)
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; CHECK: t2TEQrr renamable $r0, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.4.while.body.end:
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; CHECK: successors: %bb.5(0x04000000), %bb.1(0x7c000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next.i.14)
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; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
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; CHECK: bb.5.exit:
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; CHECK: liveins: $r0
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1
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$r2 = tMOVr $r0, 14, $noreg
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bb.1.while.begin:
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successors: %bb.5(0x04000000), %bb.2(0x7c000000)
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liveins: $r1, $r2
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renamable $r0 = t2LDRi12 renamable $r2, 4, 14, $noreg :: (load 4 from %ir.info.i)
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renamable $r0 = t2LDRHi12 killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i1)
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t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.5, 0, killed $cpsr
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bb.2.while.body.a:
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successors: %bb.5(0x04000000), %bb.3(0x7c000000)
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liveins: $r0, $r1, $r2
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renamable $r2 = t2LDRi12 killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i2)
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t2CMPri renamable $r2, 0, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.5, 0, killed $cpsr
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bb.3.it.block:
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successors: %bb.5(0x04000000), %bb.4(0x7c000000)
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liveins: $r1, $r2
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renamable $r0 = t2LDRi12 renamable $r2, 4, 14, $noreg :: (load 4 from %ir.info.i.1)
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renamable $r0 = t2LDRHi12 killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i.13)
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t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.5, 0, killed $cpsr
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bb.4.while.body.end:
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successors: %bb.5(0x04000000), %bb.1(0x7c000000)
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liveins: $r0, $r1, $r2
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renamable $r2 = t2LDRi12 killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i.14)
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t2CMPri renamable $r2, 0, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.1, 1, killed $cpsr
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bb.5.exit:
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liveins: $r0
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tBX_RET 14, $noreg, implicit $r0
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...
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