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98be3942ed
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. llvm-svn: 216225
24 lines
1.3 KiB
LLVM
24 lines
1.3 KiB
LLVM
; RUN: llc -O0 -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs < %s | FileCheck %s
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; The following 2 test cases test shufflevector with beginning UNDEF mask.
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define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
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;CHECK-LABEL: test_vext_undef_traverse:
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;CHECK: {{ext.16b.*v0, #4}}
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%vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0>, <8 x i16> %in, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9>
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ret <8 x i16> %vext
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}
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define <8 x i16> @test_vext_undef_traverse2(<8 x i16> %in) {
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;CHECK-LABEL: test_vext_undef_traverse2:
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;CHECK: {{ext.16b.*v0, #6}}
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%vext = shufflevector <8 x i16> %in, <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2>
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ret <8 x i16> %vext
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}
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define <8 x i8> @test_vext_undef_traverse3(<8 x i8> %in) {
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;CHECK-LABEL: test_vext_undef_traverse3:
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;CHECK: {{ext.8b.*v0, #6}}
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%vext = shufflevector <8 x i8> %in, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
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ret <8 x i8> %vext
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}
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