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399c8fd8d4
The AArch64 target lowering for [zs]ext of vectors is set up to handle input simple types and expects the generic SDag path to do something reasonable with anything that's not a simple type. The code, however, was only checking that the result type was a simple type and assuming that implied that the source type would also be a simple type. That's not a valid assumption, as operations like "zext <1 x i1> %0 to <1 x i32>" demonstrate. The fix is to simply explicitly validate the source type as well as the result type. PR20791 llvm-svn: 216689
28 lines
720 B
LLVM
28 lines
720 B
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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;CHECK: @func30
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;CHECK: ushll.4s v0, v0, #0
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;CHECK: movi.4s v1, #0x1
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;CHECK: and.16b v0, v0, v1
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;CHECK: str q0, [x0]
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;CHECK: ret
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%T0_30 = type <4 x i1>
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%T1_30 = type <4 x i32>
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define void @func30(%T0_30 %v0, %T1_30* %p1) {
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%r = zext %T0_30 %v0 to %T1_30
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store %T1_30 %r, %T1_30* %p1
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ret void
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}
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; Extend from v1i1 was crashing things (PR20791). Make sure we do something
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; sensible instead.
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define <1 x i32> @autogen_SD7918() {
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; CHECK-LABEL: autogen_SD7918
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; CHECK: movi d0, #0000000000000000
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; CHECK-NEXT: ret
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%I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0
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%ZE = zext <1 x i1> %I29 to <1 x i32>
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ret <1 x i32> %ZE
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}
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