Ana Pazos 6ff95d95e7 [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types ... Summary: Fixed assertions due to invalid fixup when encoding compressed instructions (c.addi, c.addiw, c.li, c.andi) with bare symbols with/without modifiers. This matches GAS behavior as well. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D52005 llvm-svn: 342160		2018-09-13 18:37:23 +00:00
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AsmParser	[RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types	2018-09-13 18:37:23 +00:00
Disassembler	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
InstPrinter
MCTargetDesc	[Target] Untangle disassemblers	2018-09-10 12:53:46 +00:00
TargetInfo
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVFrameLowering.cpp	[RISCV] Fix std::advance slowness	2018-08-24 23:13:59 +00:00
RISCVFrameLowering.h
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp
RISCVInstrInfo.h
RISCVInstrInfo.td	[RISCV] Add "lla" pseudo-instruction to assembler	2018-08-09 07:08:20 +00:00
RISCVInstrInfoA.td	[RISCV] atomic_store_nn have a different layout to regular store	2018-08-27 07:08:18 +00:00
RISCVInstrInfoC.td	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
RISCVInstrInfoD.td
RISCVInstrInfoF.td	[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode	2018-09-07 18:43:43 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp	[RISCV] Remove unused function	2018-08-17 13:40:03 +00:00
RISCVISelLowering.h	[RISCV] Remove unused function	2018-08-17 13:40:03 +00:00
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
RISCVRegisterInfo.td
RISCVSubtarget.cpp
RISCVSubtarget.h
RISCVTargetMachine.cpp
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h