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23 lines
695 B
TableGen
23 lines
695 B
TableGen
//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Tablegen register definitions common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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let Namespace = "AMDGPU" in {
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def sel_x : SubRegIndex;
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def sel_y : SubRegIndex;
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def sel_z : SubRegIndex;
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def sel_w : SubRegIndex;
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}
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include "R600RegisterInfo.td"
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include "SIRegisterInfo.td"
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