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llvm-mirror/lib/Target/AArch64
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Sander de Smalen 40471e4fe8 [AArch64][SVE] Preserve full vector regs over EH edge. 
Unwinders may only preserve the lower 64bits of Neon and SVE registers,
as only the registers in the base ABI are guaranteed to be preserved
over the exception edge. The caller will need to preserve additional
registers for when the call throws an exception and the unwinder has
tried to recover state.

For  e.g.

    svint32_t bar(svint32_t);
    svint32_t foo(svint32_t x, bool *err) {
      try { bar(x); } catch (...) { *err = true; }
      return x;
    }

`z0` needs to be spilled before the call to `bar(x)` and reloaded before
returning from foo, as the exception handler may have clobbered z0.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D84737
2020-09-02 10:54:18 +01:00
..
AsmParser [AArch64] Generate and parse SEH assembly directives 2020-08-29 15:15:22 +03:00
Disassembler [AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB 2020-06-25 15:56:36 +01:00
GISel Revert "Revert "[GlobalISel] Fold xor(cmp(pred, _, _), 1) -> cmp(inverse(pred), _, _)" (and dependent patch "Optimize away a Not feeding a brcond by using tbz instead of tbnz.")" 2020-09-01 14:29:04 -07:00
MCTargetDesc [AArch64] Generate and parse SEH assembly directives 2020-08-29 15:15:22 +03:00
TargetInfo
Utils [ARM, AArch64] Fix a comment typo. NFC. 2020-08-06 09:23:45 +03:00
AArch64.h [AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions. 2020-06-12 07:34:33 +01:00
AArch64.td [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM 2020-07-10 18:24:11 +01:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp [AArch64] Update a code comment incorrectly referring to zero_reg. NFC 2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp [DebugInfo] Update MachineInstr to help support variadic DBG_VALUE instructions 2020-06-22 16:01:12 +01:00
AArch64BranchTargets.cpp [AArch64] Fix BTI instruction emission. 2020-06-15 15:04:36 +02:00
AArch64CallingConvention.cpp [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg 2020-06-01 16:00:55 -07:00
AArch64Combine.td [GlobalISel] Add combine for (x & mask) -> x when (x & mask) == x 2020-08-19 10:20:57 -07:00
AArch64CompressJumpTables.cpp
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp DomTree: Remove getChildren() accessor 2020-07-06 21:58:11 +02:00
AArch64ConditionOptimizer.cpp MachineBasicBlock::updateTerminator now requires an explicit layout successor. 2020-06-06 22:30:51 -04:00
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp [SVE] Fix invalid assert in expand_DestructiveOp. 2020-07-04 09:21:40 +00:00
AArch64FalkorHWPFFix.cpp Prefix some AArch64/ARM passes with "aarch64-"/"arm-" 2020-07-27 11:00:39 -07:00
AArch64FastISel.cpp [FastISel] update to use intrinsic's isCommutative(); NFC 2020-08-30 11:36:41 -04:00
AArch64FrameLowering.cpp Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" 2020-09-01 19:29:03 +00:00
AArch64FrameLowering.h [AArch64][SVE] Add missing unwind info for SVE registers. 2020-08-04 11:47:06 +01:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics 2020-08-27 18:43:16 +01:00
AArch64InstrGISel.td [AArch64][GlobalISel] Add G_EXT and select ext using it 2020-06-15 12:20:59 -07:00
AArch64InstrInfo.cpp Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" 2020-09-01 19:29:03 +00:00
AArch64InstrInfo.h [AArch64][SVE] NFC: Rename isOrig -> isReverseInstr 2020-07-02 17:01:15 +01:00
AArch64InstrInfo.td [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics 2020-08-27 18:43:16 +01:00
AArch64ISelDAGToDAG.cpp [SVE] Make ElementCount members private 2020-08-28 14:43:53 +01:00
AArch64ISelLowering.cpp Strength-reduce SmallVectors to arrays. NFCI. 2020-08-28 21:14:20 +02:00
AArch64ISelLowering.h [AArch64][SVE] Add lowering for llvm fceil 2020-08-26 15:59:44 -04:00
AArch64LoadStoreOptimizer.cpp [AArch64] Fix ldst-opt of multiple disjunct subregs. 2020-06-08 20:18:24 +01:00
AArch64MachineFunctionInfo.cpp
AArch64MachineFunctionInfo.h Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" 2020-09-01 19:29:03 +00:00
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp [AArch64] Don't promote constants with float ConstantExpr. 2020-05-13 23:31:47 +01:00
AArch64RedundantCopyElimination.cpp
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp [AArch64][SVE] Preserve full vector regs over EH edge. 2020-09-02 10:54:18 +01:00
AArch64RegisterInfo.h [AArch64][SVE] Preserve full vector regs over EH edge. 2020-09-02 10:54:18 +01:00
AArch64RegisterInfo.td [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64SchedA53.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA57.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM3.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM4.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM5.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkor.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX3T110.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp [CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize 2020-08-11 12:17:10 +01:00
AArch64SelectionDAGInfo.h [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align 2020-06-30 12:46:26 +00:00
AArch64SIMDInstrOpt.cpp
AArch64SLSHardening.cpp [NFC] Clean up uses of MachineModuleInfoWrapperPass 2020-07-01 09:45:05 -07:00
AArch64SpeculationHardening.cpp
AArch64StackOffset.h [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64StackTagging.cpp [ValueTracking] Remove AllocaForValue parameter 2020-07-30 18:48:34 -07:00
AArch64StackTaggingPreRA.cpp
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
AArch64Subtarget.h [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
AArch64SVEInstrInfo.td [AArch64][SVE] Add lowering for llvm fceil 2020-08-26 15:59:44 -04:00
AArch64SystemOperands.td [AArch64] Remove inexistent system register ERXTS_EL1 2020-04-29 16:43:48 +01:00
AArch64TargetMachine.cpp [Attributes] Add a method to check if an Attribute has AttrKind None. Use instead of hasAttribute(Attribute::None) 2020-08-28 13:23:45 -07:00
AArch64TargetMachine.h Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h [llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation 2020-06-10 11:34:16 -07:00
AArch64TargetTransformInfo.cpp [Analysis] TTI: Add CastContextHint for getCastInstrCost 2020-07-29 13:32:53 +01:00
AArch64TargetTransformInfo.h [AArch64][SVE] Allow vector of pointers as legal type for masked load/store. 2020-07-31 17:30:23 -07:00
CMakeLists.txt [AArch64] Introduce AArch64SLSHardeningPass, implementing hardening of RET and BR instructions. 2020-06-11 07:51:17 +01:00
LLVMBuild.txt
SVEInstrFormats.td [AArch64][SVE] Add lowering for llvm fceil 2020-08-26 15:59:44 -04:00
SVEIntrinsicOpts.cpp [SVE] Fix bug in SVEIntrinsicOpts::optimizePTest 2020-08-14 07:57:21 +01:00