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242 lines
9.1 KiB
C++
242 lines
9.1 KiB
C++
//===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
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// JIT-compile bytecode to native PowerPC.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC32TargetMachine.h"
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#include "PPC32Relocations.h"
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#include "PowerPC.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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namespace {
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class PPC32CodeEmitter : public MachineFunctionPass {
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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/// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
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/// its address in the function into this pointer.
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void *MovePCtoLROffset;
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// Tracks which instruction references which BasicBlock
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std::vector<std::pair<const BasicBlock*,
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std::pair<unsigned*,MachineInstr*> > > BBRefs;
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// Tracks where each BasicBlock starts
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std::map<const BasicBlock*, long> BBLocations;
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/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
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///
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int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
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public:
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PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
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: TM(T), MCE(M) {}
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const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
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/// runOnMachineFunction - emits the given MachineFunction to memory
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///
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bool runOnMachineFunction(MachineFunction &MF);
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/// emitBasicBlock - emits the given MachineBasicBlock to memory
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///
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void emitBasicBlock(MachineBasicBlock &MBB);
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/// emitWord - write a 32-bit word to memory at the current PC
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///
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void emitWord(unsigned w) { MCE.emitWord(w); }
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/// getValueBit - return the particular bit of Val
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///
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unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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///
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unsigned getBinaryCodeForInstr(MachineInstr &MI);
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};
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
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/// machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE) {
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// Machine code emitter pass for PowerPC
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PM.add(new PPC32CodeEmitter(*this, MCE));
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// Delete machine code for this function after emitting it
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PM.add(createMachineCodeDeleter());
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return false;
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}
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bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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MovePCtoLROffset = 0;
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MCE.startFunction(MF);
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MCE.emitConstantPool(MF.getConstantPool());
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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emitBasicBlock(*BB);
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MCE.finishFunction(MF);
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// Resolve branches to BasicBlocks for the entire function
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for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
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intptr_t Location = BBLocations[BBRefs[i].first];
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unsigned *Ref = BBRefs[i].second.first;
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MachineInstr *MI = BBRefs[i].second.second;
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DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location
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<< " in instr: " << *MI);
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for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
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MachineOperand &op = MI->getOperand(ii);
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if (op.isPCRelativeDisp()) {
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// the instruction's branch target is made such that it branches to
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// PC + (branchTarget * 4), so undo that arithmetic here:
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// Location is the target of the branch
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// Ref is the location of the instruction, and hence the PC
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int64_t branchTarget = (Location - (long)Ref) >> 2;
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MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
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branchTarget);
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unsigned fixedInstr = PPC32CodeEmitter::getBinaryCodeForInstr(*MI);
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MCE.emitWordAt(fixedInstr, Ref);
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break;
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}
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}
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}
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BBRefs.clear();
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BBLocations.clear();
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return false;
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}
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void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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BBLocations[MBB.getBasicBlock()] = MCE.getCurrentPCValue();
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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MachineInstr &MI = *I;
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unsigned Opcode = MI.getOpcode();
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switch (MI.getOpcode()) {
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default:
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emitWord(getBinaryCodeForInstr(*I));
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break;
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case PPC::IMPLICIT_DEF:
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break; // pseudo opcode, no side effects
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case PPC::MovePCtoLR:
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assert(MovePCtoLROffset == 0 &&
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"Multiple MovePCtoLR instructions in the function?");
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MovePCtoLROffset = (void*)(intptr_t)MCE.getCurrentPCValue();
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emitWord(0x48000005); // bl 1
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break;
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}
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}
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}
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static unsigned enumRegToMachineReg(unsigned enumReg) {
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switch (enumReg) {
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case PPC::R0 : case PPC::F0 : case PPC::CR0: return 0;
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case PPC::R1 : case PPC::F1 : case PPC::CR1: return 1;
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case PPC::R2 : case PPC::F2 : case PPC::CR2: return 2;
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case PPC::R3 : case PPC::F3 : case PPC::CR3: return 3;
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case PPC::R4 : case PPC::F4 : case PPC::CR4: return 4;
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case PPC::R5 : case PPC::F5 : case PPC::CR5: return 5;
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case PPC::R6 : case PPC::F6 : case PPC::CR6: return 6;
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case PPC::R7 : case PPC::F7 : case PPC::CR7: return 7;
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case PPC::R8 : case PPC::F8 : return 8;
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case PPC::R9 : case PPC::F9 : return 9;
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case PPC::R10: case PPC::F10: return 10;
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case PPC::R11: case PPC::F11: return 11;
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case PPC::R12: case PPC::F12: return 12;
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case PPC::R13: case PPC::F13: return 13;
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case PPC::R14: case PPC::F14: return 14;
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case PPC::R15: case PPC::F15: return 15;
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case PPC::R16: case PPC::F16: return 16;
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case PPC::R17: case PPC::F17: return 17;
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case PPC::R18: case PPC::F18: return 18;
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case PPC::R19: case PPC::F19: return 19;
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case PPC::R20: case PPC::F20: return 20;
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case PPC::R21: case PPC::F21: return 21;
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case PPC::R22: case PPC::F22: return 22;
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case PPC::R23: case PPC::F23: return 23;
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case PPC::R24: case PPC::F24: return 24;
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case PPC::R25: case PPC::F25: return 25;
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case PPC::R26: case PPC::F26: return 26;
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case PPC::R27: case PPC::F27: return 27;
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case PPC::R28: case PPC::F28: return 28;
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case PPC::R29: case PPC::F29: return 29;
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case PPC::R30: case PPC::F30: return 30;
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case PPC::R31: case PPC::F31: return 31;
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default:
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std::cerr << "Unhandled reg in enumRegToRealReg!\n";
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abort();
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}
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}
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int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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int rv = 0; // Return value; defaults to 0 for unhandled cases
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// or things that get fixed up later by the JIT.
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if (MO.isRegister()) {
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rv = enumRegToMachineReg(MO.getReg());
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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} else if (MO.isGlobalAddress()) {
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unsigned Reloc = 0;
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if (MI.getOpcode() == PPC::CALLpcrel)
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Reloc = PPC::reloc_pcrel_bx;
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else if (MI.getOpcode() == PPC::LOADHiAddr) {
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Reloc = PPC::reloc_absolute_loadhi;
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} else if (MI.getOpcode() == PPC::LA) {
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Reloc = PPC::reloc_absolute_la;
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} else {
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assert(0 && "Unknown instruction for relocation!");
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}
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MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
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Reloc, MO.getGlobal(),
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-((intptr_t)MovePCtoLROffset+4)));
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} else if (MO.isMachineBasicBlock()) {
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const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
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unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
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BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
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} else if (MO.isConstantPoolIndex()) {
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unsigned index = MO.getConstantPoolIndex();
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rv = MCE.getConstantPoolEntryAddress(index);
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} else {
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std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
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abort();
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}
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// Special treatment for global symbols: constants and vars
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if ((MO.isConstantPoolIndex() || MO.isGlobalAddress()) &&
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MI.getOpcode() != PPC::CALLpcrel) {
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unsigned Opcode = MI.getOpcode();
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assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
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if (Opcode == PPC::LOADHiAddr) {
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// LoadHiAddr wants hi16(addr - &MovePCtoLR)
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rv >>= 16;
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} else if (Opcode == PPC::LWZ || Opcode == PPC::LA ||
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Opcode == PPC::LFS || Opcode == PPC::LFD) {
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// These load opcodes want lo16(addr - &MovePCtoLR)
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rv &= 0xffff;
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}
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}
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return rv;
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}
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#include "PPC32GenCodeEmitter.inc"
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