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d5ccdcd01b
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. llvm-svn: 194094
65 lines
2.1 KiB
ArmAsm
65 lines
2.1 KiB
ArmAsm
@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv6-apple-darwin -mcpu=cortex-m0 -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s > %t 2> %t2
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@ RUN: FileCheck %s --check-prefix=CHECK-EVIL-PRE-UAL < %t
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@ RUN: FileCheck %s --check-prefix CHECK-ERROR < %t2
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.syntax unified
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nop
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yield
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wfe
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wfi
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sev
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@ CHECK: nop @ encoding: [0x00,0xbf]
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@ CHECK: yield @ encoding: [0x10,0xbf]
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@ CHECK: wfe @ encoding: [0x20,0xbf]
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@ CHECK: wfi @ encoding: [0x30,0xbf]
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@ CHECK: sev @ encoding: [0x40,0xbf]
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@ CHECK-EVIL-PRE-UAL: mov r8, r8 @ encoding: [0xc0,0x46]
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dmb sy
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dmb
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dsb sy
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dsb
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isb sy
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isb
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@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
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@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
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@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f]
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@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f]
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@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
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@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
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@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
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@ CHECK-ERROR-NEXT: yield
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@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
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@ CHECK-ERROR-NEXT: wfe
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@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
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@ CHECK-ERROR-NEXT: wfi
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@ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
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@ CHECK-ERROR-NEXT: sev
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@ CHECK-ERROR: error:
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@ CHECK-ERROR-NEXT: dmb sy
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@ CHECK-ERROR: error: instruction requires: data-barriers
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@ CHECK-ERROR-NEXT: dmb
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@ CHECK-ERROR: error:
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@ CHECK-ERROR-NEXT: dsb sy
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@ CHECK-ERROR: error: instruction requires: data-barriers
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@ CHECK-ERROR-NEXT: dsb
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@ CHECK-ERROR: error:
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@ CHECK-ERROR-NEXT: isb sy
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@ CHECK-ERROR: error: instruction requires: data-barriers
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@ CHECK-ERROR-NEXT: isb
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