Alex Bradbury 5a992b5fc4 [TableGen] Give the option of tolerating duplicate register names ... A number of architectures re-use the same register names (e.g. for both 32-bit FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated MatchRegisterName and MatchRegisterAltName, as tablegen (when built with asserts enabled) will fail. When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register names will be tolerated. A backend can then coerce registers to the desired register class by (for instance) implementing validateTargetOperandClass. At least the in-tree Sparc backend could benefit from this, as does RISC-V (single and double precision floating point registers). Differential Revision: https://reviews.llvm.org/D39845 llvm-svn: 320018		2017-12-07 09:51:55 +00:00
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GlobalISel	Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.	2017-12-05 05:52:07 +00:00
GenericOpcodes.td	Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.	2017-12-05 05:52:07 +00:00
Target.td	[TableGen] Give the option of tolerating duplicate register names	2017-12-07 09:51:55 +00:00
TargetCallingConv.td	Swift Calling Convention: add swifterror attribute.	2016-04-01 21:41:15 +00:00
TargetIntrinsicInfo.h	GlobalISel: support translation of intrinsic calls.	2016-07-29 22:32:36 +00:00
TargetItinerary.td	Fix comment typos. NFC.	2016-11-20 13:47:59 +00:00
TargetMachine.h	Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"	2017-10-12 22:57:28 +00:00
TargetOptions.h	[MC] Function stack size section.	2017-11-30 13:05:14 +00:00
TargetSchedule.td	Fix comment typos.	2017-05-08 15:33:08 +00:00
TargetSelectionDAG.td	[globalisel][tablegen] Add support for relative AtomicOrderings	2017-11-30 21:05:59 +00:00