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bc658bf60a
This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196 |
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| .. | ||
| directive-insn.s | ||
| fixups-zEC12.s | ||
| fixups.s | ||
| insn-bad-z13.s | ||
| insn-bad-z14.s | ||
| insn-bad-z196.s | ||
| insn-bad-zEC12.s | ||
| insn-bad.s | ||
| insn-good-z13.s | ||
| insn-good-z14.s | ||
| insn-good-z196.s | ||
| insn-good-zEC12.s | ||
| insn-good.s | ||
| lit.local.cfg | ||
| regs-bad.s | ||
| regs-good.s | ||
| tokens.s | ||
| word.s | ||