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ce1573aa8c
Some EVEX instructions should check the predicates when compress to VEX encoding. For example, avx512vnni instructions. This is because avx512vnni doesn't mean that avxvnni is supported on the target. This patch moving the manually added check to .inc that generated by tablegen. Differential Revision: https://reviews.llvm.org/D98011
276 lines
10 KiB
C++
276 lines
10 KiB
C++
//===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
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/// compression tables.
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///
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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namespace {
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class X86EVEX2VEXTablesEmitter {
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RecordKeeper &Records;
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CodeGenTarget Target;
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// Hold all non-masked & non-broadcasted EVEX encoded instructions
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std::vector<const CodeGenInstruction *> EVEXInsts;
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// Hold all VEX encoded instructions. Divided into groups with same opcodes
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// to make the search more efficient
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std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
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typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
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typedef std::pair<StringRef, StringRef> Predicate;
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// Represent both compress tables
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std::vector<Entry> EVEX2VEX128;
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std::vector<Entry> EVEX2VEX256;
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// Represent predicates of VEX instructions.
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std::vector<Predicate> EVEX2VEXPredicates;
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public:
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X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
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// run - Output X86 EVEX2VEX tables.
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void run(raw_ostream &OS);
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private:
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// Prints the given table as a C++ array of type
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// X86EvexToVexCompressTableEntry
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void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
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// Prints function which checks target feature specific predicate.
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void printCheckPredicate(const std::vector<Predicate> &Predicates,
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raw_ostream &OS);
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};
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void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
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raw_ostream &OS) {
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StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
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OS << "// X86 EVEX encoded instructions that have a VEX " << Size
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<< " encoding\n"
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<< "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
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<< "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
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<< "CompressTable[] = {\n"
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<< " // EVEX scalar with corresponding VEX.\n";
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// Print all entries added to the table
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for (auto Pair : Table) {
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OS << " { X86::" << Pair.first->TheDef->getName()
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<< ", X86::" << Pair.second->TheDef->getName() << " },\n";
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}
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OS << "};\n\n";
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}
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void X86EVEX2VEXTablesEmitter::printCheckPredicate(
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const std::vector<Predicate> &Predicates, raw_ostream &OS) {
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OS << "static bool CheckVEXInstPredicate"
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<< "(MachineInstr &MI, const X86Subtarget *Subtarget) {\n"
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<< " unsigned Opc = MI.getOpcode();\n"
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<< " switch (Opc) {\n"
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<< " default: return true;\n";
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for (auto Pair : Predicates)
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OS << " case X86::" << Pair.first << ": return " << Pair.second << ";\n";
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OS << " }\n"
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<< "}\n\n";
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}
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// Return true if the 2 BitsInits are equal
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// Calculates the integer value residing BitsInit object
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static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
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uint64_t Value = 0;
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for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
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if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
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Value |= uint64_t(Bit->getValue()) << i;
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else
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PrintFatalError("Invalid VectSize bit");
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}
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return Value;
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}
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// Function object - Operator() returns true if the given VEX instruction
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// matches the EVEX instruction of this object.
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class IsMatch {
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const CodeGenInstruction *EVEXInst;
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public:
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IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
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bool operator()(const CodeGenInstruction *VEXInst) {
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Record *RecE = EVEXInst->TheDef;
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Record *RecV = VEXInst->TheDef;
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bool EVEX_W = RecE->getValueAsBit("HasVEX_W");
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bool VEX_W = RecV->getValueAsBit("HasVEX_W");
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bool VEX_WIG = RecV->getValueAsBit("IgnoresVEX_W");
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bool EVEX_WIG = RecE->getValueAsBit("IgnoresVEX_W");
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bool EVEX_W1_VEX_W0 = RecE->getValueAsBit("EVEX_W1_VEX_W0");
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if (RecV->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
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RecV->getValueAsBit("isCodeGenOnly") != RecE->getValueAsBit("isCodeGenOnly") ||
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// VEX/EVEX fields
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RecV->getValueAsDef("OpPrefix") != RecE->getValueAsDef("OpPrefix") ||
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RecV->getValueAsDef("OpMap") != RecE->getValueAsDef("OpMap") ||
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RecV->getValueAsBit("hasVEX_4V") != RecE->getValueAsBit("hasVEX_4V") ||
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RecV->getValueAsBit("hasEVEX_L2") != RecE->getValueAsBit("hasEVEX_L2") ||
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RecV->getValueAsBit("hasVEX_L") != RecE->getValueAsBit("hasVEX_L") ||
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// Match is allowed if either is VEX_WIG, or they match, or EVEX
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// is VEX_W1X and VEX is VEX_W0.
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(!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
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(EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
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// Instruction's format
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RecV->getValueAsDef("Form") != RecE->getValueAsDef("Form"))
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return false;
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// This is needed for instructions with intrinsic version (_Int).
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// Where the only difference is the size of the operands.
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// For example: VUCOMISDZrm and Int_VUCOMISDrm
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// Also for instructions that their EVEX version was upgraded to work with
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// k-registers. For example VPCMPEQBrm (xmm output register) and
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// VPCMPEQBZ128rm (k register output register).
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for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
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Record *OpRec1 = EVEXInst->Operands[i].Rec;
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Record *OpRec2 = VEXInst->Operands[i].Rec;
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if (OpRec1 == OpRec2)
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continue;
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if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
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if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
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return false;
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} else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
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return false;
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} else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
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if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
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return false;
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}
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} else
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return false;
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}
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return true;
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}
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private:
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static inline bool isRegisterOperand(const Record *Rec) {
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return Rec->isSubClassOf("RegisterClass") ||
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Rec->isSubClassOf("RegisterOperand");
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}
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static inline bool isMemoryOperand(const Record *Rec) {
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return Rec->isSubClassOf("Operand") &&
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Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
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}
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static inline bool isImmediateOperand(const Record *Rec) {
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return Rec->isSubClassOf("Operand") &&
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Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
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}
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static inline unsigned int getRegOperandSize(const Record *RegRec) {
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if (RegRec->isSubClassOf("RegisterClass"))
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return RegRec->getValueAsInt("Alignment");
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if (RegRec->isSubClassOf("RegisterOperand"))
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return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
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llvm_unreachable("Register operand's size not known!");
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}
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};
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void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
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auto getPredicates = [&](const CodeGenInstruction *Inst) {
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std::vector<Record *> PredicatesRecords =
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Inst->TheDef->getValueAsListOfDefs("Predicates");
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// Currently we only do AVX related checks and assume each instruction
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// has one and only one AVX related predicates.
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for (unsigned i = 0, e = PredicatesRecords.size(); i != e; ++i)
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if (PredicatesRecords[i]->getName().startswith("HasAVX"))
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return PredicatesRecords[i]->getValueAsString("CondString");
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llvm_unreachable(
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"Instruction with checkPredicate set must have one predicate!");
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};
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emitSourceFileHeader("X86 EVEX2VEX tables", OS);
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ArrayRef<const CodeGenInstruction *> NumberedInstructions =
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Target.getInstructionsByEnumValue();
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for (const CodeGenInstruction *Inst : NumberedInstructions) {
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// Filter non-X86 instructions.
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if (!Inst->TheDef->isSubClassOf("X86Inst"))
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continue;
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// Add VEX encoded instructions to one of VEXInsts vectors according to
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// it's opcode.
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if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
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uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
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getValueAsBitsInit("Opcode"));
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VEXInsts[Opcode].push_back(Inst);
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}
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// Add relevant EVEX encoded instructions to EVEXInsts
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else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
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!Inst->TheDef->getValueAsBit("hasEVEX_K") &&
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!Inst->TheDef->getValueAsBit("hasEVEX_B") &&
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!Inst->TheDef->getValueAsBit("hasEVEX_L2") &&
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!Inst->TheDef->getValueAsBit("notEVEX2VEXConvertible"))
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EVEXInsts.push_back(Inst);
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}
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for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
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uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
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getValueAsBitsInit("Opcode"));
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// For each EVEX instruction look for a VEX match in the appropriate vector
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// (instructions with the same opcode) using function object IsMatch.
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// Allow EVEX2VEXOverride to explicitly specify a match.
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const CodeGenInstruction *VEXInst = nullptr;
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if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
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StringRef AltInstStr =
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EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
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Record *AltInstRec = Records.getDef(AltInstStr);
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assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
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VEXInst = &Target.getInstruction(AltInstRec);
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} else {
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auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
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if (Match != VEXInsts[Opcode].end())
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VEXInst = *Match;
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}
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if (!VEXInst)
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continue;
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// In case a match is found add new entry to the appropriate table
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if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
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EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
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else
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EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
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// Adding predicate check to EVEX2VEXPredicates table when needed.
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if (VEXInst->TheDef->getValueAsBit("checkVEXPredicate"))
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EVEX2VEXPredicates.push_back(
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std::make_pair(EVEXInst->TheDef->getName(), getPredicates(VEXInst)));
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}
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// Print both tables
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printTable(EVEX2VEX128, OS);
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printTable(EVEX2VEX256, OS);
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// Print CheckVEXInstPredicate function.
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printCheckPredicate(EVEX2VEXPredicates, OS);
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}
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}
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namespace llvm {
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void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
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X86EVEX2VEXTablesEmitter(RK).run(OS);
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}
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}
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