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59de807f62
This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
134 lines
4.5 KiB
YAML
134 lines
4.5 KiB
YAML
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
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# With one version of the D48102 fix, this test failed with
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# Assertion failed: (ValNo && "CopyMI input register not live"), function reMaterializeTrivialDef, file ../lib/CodeGen/RegisterCoalescer.cpp, line 1107.
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# GCN: {{^body}}
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--- |
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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target triple = "amdgcn--amdpal"
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define amdgpu_cs void @_amdgpu_cs_main(<3 x i32>) #0 {
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="gfx803" }
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...
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---
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name: _amdgpu_cs_main
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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%0:vgpr_32 = nofpexcept V_MUL_F32_e32 0, undef %1:vgpr_32, implicit $mode, implicit $exec
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%2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %0, implicit $mode, implicit $exec
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%3:vgpr_32 = nofpexcept V_CVT_F32_I32_e32 killed %2, implicit $mode, implicit $exec
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%4:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %3, implicit $mode, implicit $exec
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%5:vgpr_32 = V_LSHRREV_B32_e32 4, killed %4, implicit $exec
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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bb.1:
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successors: %bb.5(0x80000000)
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undef %6.sub1:vreg_128 = COPY killed %5
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%7:vreg_128 = COPY killed %6
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S_BRANCH %bb.5
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bb.2:
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successors: %bb.3(0x40000000), %bb.4(0x40000000)
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S_CBRANCH_SCC0 %bb.4, implicit undef $scc
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bb.3:
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successors: %bb.5(0x80000000)
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%8:sreg_32_xm0 = S_MOV_B32 0
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undef %9.sub0:sgpr_128 = COPY %8
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%9.sub1:sgpr_128 = COPY %8
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%9.sub2:sgpr_128 = COPY %8
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%9.sub3:sgpr_128 = COPY killed %8
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%10:vreg_128 = COPY killed %9
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%7:vreg_128 = COPY killed %10
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S_BRANCH %bb.5
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bb.4:
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successors: %bb.5(0x80000000)
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%11:sreg_32_xm0 = S_MOV_B32 0
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undef %12.sub0:sgpr_128 = COPY %11
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%12.sub1:sgpr_128 = COPY %11
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%12.sub2:sgpr_128 = COPY %11
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%12.sub3:sgpr_128 = COPY killed %11
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%13:sgpr_128 = COPY killed %12
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%14:vreg_128 = COPY killed %13
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%7:vreg_128 = COPY killed %14
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bb.5:
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successors: %bb.8(0x40000000), %bb.6(0x40000000)
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%15:vreg_128 = COPY killed %7
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S_CBRANCH_SCC0 %bb.8, implicit undef $scc
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bb.6:
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successors: %bb.7(0x80000000)
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%16:vreg_128 = COPY killed %15
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bb.7:
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successors: %bb.14(0x80000000)
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%17:vreg_128 = COPY killed %16
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S_BRANCH %bb.14
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bb.8:
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successors: %bb.9(0x40000000), %bb.11(0x40000000)
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%18:vgpr_32 = V_MUL_LO_I32 %15.sub1, target-flags(amdgpu-gotprel32-lo) 7, implicit $exec
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S_CBRANCH_SCC1 %bb.11, implicit undef $scc
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S_BRANCH %bb.9
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bb.9:
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successors: %bb.10(0x80000000)
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%19:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %18, undef %20:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
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%21:sreg_64 = V_CMP_NE_U32_e64 target-flags(amdgpu-gotprel) 0, killed %19.sub0, implicit $exec
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%22:sreg_64 = COPY $exec, implicit-def $exec
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%23:sreg_64 = S_AND_B64 %22, %21, implicit-def dead $scc
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$exec = S_MOV_B64_term killed %23
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bb.10:
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successors: %bb.12(0x80000000)
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$exec = S_OR_B64 $exec, killed %22, implicit-def $scc
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S_BRANCH %bb.12
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bb.11:
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successors: %bb.13(0x80000000)
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%24:vreg_128 = COPY killed %15
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%24.sub0:vreg_128 = COPY undef %18
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S_BRANCH %bb.13
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bb.12:
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successors: %bb.11(0x80000000)
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S_BRANCH %bb.11
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bb.13:
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successors: %bb.7(0x80000000)
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%16:vreg_128 = COPY killed %24
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S_BRANCH %bb.7
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bb.14:
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successors: %bb.15(0x80000000)
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S_CBRANCH_SCC1 %bb.15, implicit undef $scc
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S_BRANCH %bb.15
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bb.15:
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undef %25.sub2:vreg_128 = COPY killed %17.sub2
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%26:sreg_32_xm0 = S_MOV_B32 0
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undef %27.sub0:sgpr_256 = COPY %26
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%27.sub1:sgpr_256 = COPY %26
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%27.sub2:sgpr_256 = COPY %26
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%27.sub3:sgpr_256 = COPY %26
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%27.sub4:sgpr_256 = COPY %26
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%27.sub5:sgpr_256 = COPY %26
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%27.sub6:sgpr_256 = COPY %26
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%27.sub7:sgpr_256 = COPY killed %26
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%28:vgpr_32 = IMAGE_LOAD_V1_V4 killed %25, killed %27, 2, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
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%29:vgpr_32 = nofpexcept V_ADD_F32_e32 0, killed %28, implicit $mode, implicit $exec
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$m0 = S_MOV_B32 -1
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DS_WRITE_B32 undef %30:vgpr_32, killed %29, 0, 0, implicit $m0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`, addrspace 3)
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S_ENDPGM 0
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...
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