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6705a324ed
The hardware has created a real mess in the naming for add/sub, which have been renamed basically every generation. Switch the carry out pseudos to have the gfx9/gfx10 names. We were using the original SI/CI v_add_i32/v_sub_i32 names. Later targets reintroduced these names as carryless instructions with a saturating clamp bit, which we do not define. Do this rename so we can unambiguously add these missing instructions. The carry-in versions should also be renamed, but at least those had a consistent _u32 name to begin with. The 16-bit instructions were also renamed, but aren't ambiguous. This does regress assembler error message quality in some cases. In mismatched wave32/wave64 situations, this will switch from "unsupported instruction" to "invalid operand", with the error pointing at the wrong position. I couldn't quite follow how the assembler selects these, but the previous behavior seemed accidental to me. It looked like there was a partial attempt to handle this which was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it isn't used for anything).
51 lines
2.9 KiB
YAML
51 lines
2.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: s_add_co_pseudo_test
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0, $sgpr1, $sgpr2
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; GCN-LABEL: name: s_add_co_pseudo_test
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; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0, $sgpr1, $sgpr2
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[COPY6:%[0-9]+]]:sgpr_32 = COPY [[COPY3]]
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; GCN: [[V_MUL_LO_U32_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[COPY]], [[COPY4]], implicit $exec
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; GCN: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 killed [[V_MUL_LO_U32_]], [[COPY6]], 0, implicit $exec
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; GCN: [[S_MUL_HI_U32_:%[0-9]+]]:sreg_32 = S_MUL_HI_U32 [[COPY4]], [[COPY5]]
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -614296167
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; GCN: [[V_MUL_LO_U32_1:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[COPY]], [[COPY3]], implicit $exec
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; GCN: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_]]
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; GCN: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 killed [[V_MUL_LO_U32_1]], [[COPY7]], [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
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; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY4]], [[V_ADDC_U32_e64_]], implicit $exec
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; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -181084736
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; GCN: [[V_MUL_LO_U32_2:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[V_MUL_HI_U32_]], [[S_MOV_B32_1]], implicit $exec
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; GCN: [[COPY8:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_1]]
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; GCN: [[V_ADDC_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[COPY8]], killed [[V_MUL_LO_U32_2]], [[V_ADDC_U32_e64_1]], 0, implicit $exec
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%0:vgpr_32 = COPY $vgpr0
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%6:sreg_32 = COPY %0
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr2
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%3:sreg_32 = COPY $sgpr0
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%4:sreg_32 = COPY $sgpr1
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%5:sreg_32 = COPY $sgpr2
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%20:vgpr_32 = COPY %3
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%7:sreg_32 = S_MUL_I32 %6, %4
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%9:vgpr_32, %10:sreg_64_xexec = V_ADD_CO_U32_e64 killed %7, %20, 0, implicit $exec
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%8:sreg_32 = S_MUL_HI_U32 %4, %5
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%11:sreg_32 = S_MOV_B32 -614296167
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%12:sreg_32 = S_MUL_I32 %6, %3
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%14:sreg_32, %13:sreg_64_xexec = S_ADD_CO_PSEUDO killed %12, killed %11, killed %10, implicit-def dead $scc
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%15:sreg_32 = S_MUL_HI_U32 %4, %14
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%16:sreg_32 = S_MOV_B32 -181084736
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%17:sreg_32 = S_MUL_I32 %15, %16
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%19:sreg_32, %18:sreg_64_xexec = S_ADD_CO_PSEUDO killed %16, killed %17, killed %13, implicit-def dead $scc
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...
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