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https://github.com/RPCS3/llvm-mirror.git
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dd82110acb
This was only used for matching the saddr addressing mode of global instructions, but this was not implemented correctly. The instruction definitions aren't even correct, and are defined as using a 64-bit VGPR component. Eliminate this pass to enable correcting the instruction definitions. A new matching implementation can work in GlobalISel or relying on DAG divergence information for the base address.
323 lines
14 KiB
LLVM
323 lines
14 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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@stored_lds_ptr = addrspace(3) global i32 addrspace(3)* undef, align 4
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@stored_constant_ptr = addrspace(3) global i32 addrspace(4)* undef, align 8
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@stored_global_ptr = addrspace(3) global i32 addrspace(1)* undef, align 8
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; GCN-LABEL: {{^}}reorder_local_load_global_store_local_load:
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; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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; GFX9: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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store i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_reorder_local_load_volatile_global_store_local_load:
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; CI: buffer_store_dword
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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; GFX9: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; GFX9: global_store_dword
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; GFX9: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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define amdgpu_kernel void @no_reorder_local_load_volatile_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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store volatile i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_reorder_barrier_local_load_global_store_local_load:
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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; CI: buffer_store_dword
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; GFX9-DAG: global_store_dword
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; GFX9-DAG: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; GFX9: s_barrier
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; GFX9-DAG: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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; GFX9-DAG: global_store_dword
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define amdgpu_kernel void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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store i32 99, i32 addrspace(1)* %gptr, align 4
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call void @llvm.amdgcn.s.barrier() #1
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%tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_constant_load_global_store_constant_load:
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; GCN-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1
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; CI: buffer_store_dword
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; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3
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; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4
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; GFX9: global_store_dword
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; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8
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%ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 3
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%tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4
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store i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_constant_load_local_store_constant_load:
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; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1
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; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3
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; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4
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; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc
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; GCN-DAG: ds_write_b32
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 {
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%ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8
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%ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 3
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%tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4
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store i32 99, i32 addrspace(3)* %lptr, align 4
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%tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_smrd_load_local_store_smrd_load:
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; GCN: s_load_dword
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; GCN: s_load_dword
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; GCN: s_load_dword
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; GCN: ds_write_b32
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_smrd_load_local_store_smrd_load(i32 addrspace(1)* %out, i32 addrspace(3)* noalias %lptr, i32 addrspace(4)* %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 2
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%tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4
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store i32 99, i32 addrspace(3)* %lptr, align 4
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%tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_global_load_local_store_global_load:
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; CI: ds_write_b32
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; CI: buffer_load_dword
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; CI: buffer_load_dword
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; CI: buffer_store_dword
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; GFX9: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:4
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; GFX9: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:12
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; GFX9: ds_write_b32
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define amdgpu_kernel void @reorder_global_load_local_store_global_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr, i32 addrspace(1)* %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 3
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%tmp1 = load i32, i32 addrspace(1)* %ptr1, align 4
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store i32 99, i32 addrspace(3)* %lptr, align 4
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%tmp2 = load i32, i32 addrspace(1)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_local_offsets:
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; GCN: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:100 offset1:102
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; GCN-DAG: ds_write2_b32 {{v[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:3 offset1:100
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; GCN-DAG: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:408
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(3)* noalias nocapture %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 100
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%ptr3 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 102
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store i32 123, i32 addrspace(3)* %ptr1, align 4
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%tmp1 = load i32, i32 addrspace(3)* %ptr2, align 4
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%tmp2 = load i32, i32 addrspace(3)* %ptr3, align 4
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store i32 123, i32 addrspace(3)* %ptr2, align 4
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%tmp3 = load i32, i32 addrspace(3)* %ptr1, align 4
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store i32 789, i32 addrspace(3)* %ptr3, align 4
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%add.0 = add nsw i32 %tmp2, %tmp1
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%add.1 = add nsw i32 %add.0, %tmp3
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store i32 %add.1, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_global_offsets:
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; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
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; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
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; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12
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; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
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; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
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; CI: buffer_store_dword
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; CI: s_endpgm
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; GFX9-DAG: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:400
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; GFX9-DAG: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:408
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; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, off offset:12
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; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, off offset:400
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; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, off offset:408
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; GFX9: global_store_dword
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; GFX9: s_endpgm
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define amdgpu_kernel void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(1)* noalias nocapture %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3
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%ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 100
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%ptr3 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 102
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store i32 123, i32 addrspace(1)* %ptr1, align 4
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%tmp1 = load i32, i32 addrspace(1)* %ptr2, align 4
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%tmp2 = load i32, i32 addrspace(1)* %ptr3, align 4
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store i32 123, i32 addrspace(1)* %ptr2, align 4
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%tmp3 = load i32, i32 addrspace(1)* %ptr1, align 4
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store i32 789, i32 addrspace(1)* %ptr3, align 4
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%add.0 = add nsw i32 %tmp2, %tmp1
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%add.1 = add nsw i32 %add.0, %tmp3
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store i32 %add.1, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_global_offsets_addr64_soffset0:
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; CI: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
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; CI-NEXT: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:28{{$}}
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; CI-NEXT: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:44{{$}}
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; CI: v_mov_b32
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; CI: v_mov_b32
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; CI: v_add_i32
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; CI: v_add_i32
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; CI: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CI: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20{{$}}
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; CI: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:36{{$}}
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; CI-NEXT: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:52{{$}}
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; GFX9: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:12
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; GFX9: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:28
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; GFX9: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:44
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off{{$}}
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off offset:20
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off offset:36
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off offset:52
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define amdgpu_kernel void @reorder_global_offsets_addr64_soffset0(i32 addrspace(1)* noalias nocapture %ptr.base) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%ptr0 = getelementptr inbounds i32, i32 addrspace(1)* %ptr.base, i64 %id.ext
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%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3
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%ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 5
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%ptr3 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 7
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%ptr4 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 9
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%ptr5 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 11
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%ptr6 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 13
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store i32 789, i32 addrspace(1)* %ptr0, align 4
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%tmp1 = load i32, i32 addrspace(1)* %ptr1, align 4
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store i32 123, i32 addrspace(1)* %ptr2, align 4
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%tmp2 = load i32, i32 addrspace(1)* %ptr3, align 4
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%add.0 = add nsw i32 %tmp1, %tmp2
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store i32 %add.0, i32 addrspace(1)* %ptr4, align 4
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%tmp3 = load i32, i32 addrspace(1)* %ptr5, align 4
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%add.1 = add nsw i32 %add.0, %tmp3
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store i32 %add.1, i32 addrspace(1)* %ptr6, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_local_load_tbuffer_store_local_load:
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; GCN: tbuffer_store_format
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; GCN: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:2
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define amdgpu_vs void @reorder_local_load_tbuffer_store_local_load(i32 addrspace(1)* %out, i32 %a1, i32 %vaddr) #0 {
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%ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2
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%tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
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%vaddr.add = add i32 %vaddr, 32
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call void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32> %vdata, <4 x i32> undef, i32 %vaddr.add, i32 0, i32 0, i32 228, i32 3)
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%tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare void @llvm.amdgcn.s.barrier() #1
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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declare void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32 immarg, i32 immarg) #3
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attributes #0 = { nounwind }
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attributes #1 = { convergent nounwind willreturn }
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attributes #2 = { nounwind readnone speculatable willreturn }
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attributes #3 = { nounwind willreturn writeonly }
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