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acf8746c63
The selection process being split into separate passes, we need generic opcodes to translate the LLVM IR to target independent code. This patch adds an opcode for addition: G_ADD. Differential Revision: http://reviews.llvm.org/D15472 llvm-svn: 258333
45 lines
1.6 KiB
TableGen
45 lines
1.6 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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class TestInstruction : Instruction {
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let Size = 1;
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let OutOperandList = (outs);
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let InOperandList = (ins);
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field bits<8> Inst;
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field bits<8> SoftFail = 0;
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}
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def InstA : TestInstruction {
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let Inst = {0,0,0,0,0,0,?,?};
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let AsmString = "InstA";
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let DecoderMethod = "DecodeInstA";
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let hasCompleteDecoder = 0;
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}
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def InstB : TestInstruction {
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let Inst = {0,0,0,?,?,0,1,1};
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let AsmString = "InstB";
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let DecoderMethod = "DecodeInstB";
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let hasCompleteDecoder = 0;
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}
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// CHECK: /* 0 */ MCD::OPC_ExtractField, 2, 1, // Inst{2} ...
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// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 29, 0, // Skip to: 36
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// CHECK-NEXT: /* 7 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ...
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// CHECK-NEXT: /* 10 */ MCD::OPC_FilterValue, 0, 22, 0, // Skip to: 36
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// CHECK-NEXT: /* 14 */ MCD::OPC_CheckField, 0, 2, 3, 5, 0, // Skip to: 25
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// CHECK-NEXT: /* 20 */ MCD::OPC_TryDecode, 25, 0, 0, 0, // Opcode: InstB, skip to: 25
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// CHECK-NEXT: /* 25 */ MCD::OPC_CheckField, 3, 2, 0, 5, 0, // Skip to: 36
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// CHECK-NEXT: /* 31 */ MCD::OPC_TryDecode, 24, 1, 0, 0, // Opcode: InstA, skip to: 36
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// CHECK-NEXT: /* 36 */ MCD::OPC_Fail,
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// CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
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// CHECK: if (DecodeInstA(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
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