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7464e6c913
This patch moves the construction of the default backend from llvm-mca.cpp and into mca::Context. The Context class is responsible for holding ownership of the simulated hardware components. These components are subclasses of HardwareUnit. Right now the HardwareUnit is pretty bare-bones, but eventually we might want to add some common functionality across all hardware components, such as isReady() or something similar. I have a feeling this patch will probably need some updates, but it's a start. One thing I am not particularly fond of is the rather large interface for createDefaultPipeline. That convenience routine takes a rather large set of inputs from the llvm-mca driver, where many of those inputs are generated via command line options. One item I think we might want to change is the separating of ownership of hardware components (owned by the context) and the pipeline (which owns Stages). In short, a Pipeline owns Stages, a Context (currently) owns hardware. The Pipeline's Stages make use of the components, and thus there is a lifetime dependency generated. The components must outlive the pipeline. We could solve this by having the Context also own the Pipeline, and not return a unique_ptr<Pipeline>. Now that I think about it, I like that idea more. Differential Revision: https://reviews.llvm.org/D48691 llvm-svn: 336456
66 lines
2.2 KiB
C++
66 lines
2.2 KiB
C++
//===---------------------------- Context.cpp -------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a class for holding ownership of various simulated
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/// hardware units. A Context also provides a utility routine for constructing
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/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
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/// stages).
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///
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//===----------------------------------------------------------------------===//
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#include "Context.h"
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#include "DispatchStage.h"
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#include "ExecuteStage.h"
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#include "FetchStage.h"
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#include "RegisterFile.h"
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#include "RetireControlUnit.h"
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#include "RetireStage.h"
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#include "Scheduler.h"
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namespace mca {
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using namespace llvm;
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std::unique_ptr<Pipeline>
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Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
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SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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// Create the hardware units defining the backend.
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auto RCU = llvm::make_unique<RetireControlUnit>(SM);
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auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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auto HWS = llvm::make_unique<Scheduler>(
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SM, Opts.LoadQueueSize, Opts.StoreQueueSize, Opts.AssumeNoAlias);
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// Create the pipeline and its stages.
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auto P = llvm::make_unique<Pipeline>(
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Opts.DispatchWidth, Opts.RegisterFileSize, Opts.LoadQueueSize,
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Opts.StoreQueueSize, Opts.AssumeNoAlias);
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auto F = llvm::make_unique<FetchStage>(IB, SrcMgr);
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auto D = llvm::make_unique<DispatchStage>(
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STI, MRI, Opts.RegisterFileSize, Opts.DispatchWidth, *RCU, *PRF, *HWS);
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auto R = llvm::make_unique<RetireStage>(*RCU, *PRF);
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auto E = llvm::make_unique<ExecuteStage>(*RCU, *HWS);
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// Add the hardware to the context.
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addHardwareUnit(std::move(RCU));
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addHardwareUnit(std::move(PRF));
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addHardwareUnit(std::move(HWS));
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// Build the pipeline.
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P->appendStage(std::move(F));
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P->appendStage(std::move(D));
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P->appendStage(std::move(R));
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P->appendStage(std::move(E));
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return P;
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}
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} // namespace mca
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