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https://github.com/RPCS3/llvm-mirror.git
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1977275dcd
By moving this transform to InstSimplify from InstCombine, we sidestep the problem/question raised by PR27869: https://llvm.org/bugs/show_bug.cgi?id=27869 ...where InstCombine turns an icmp+zext into a shift causing us to miss the fold. Credit to David Majnemer for a draft patch of the changes to InstructionSimplify.cpp. Differential Revision: http://reviews.llvm.org/D21512 llvm-svn: 273200
346 lines
7.8 KiB
LLVM
346 lines
7.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instsimplify -S | FileCheck %s
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define i64 @pow2(i32 %x) {
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; CHECK-LABEL: @pow2(
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; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, %x
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; CHECK-NEXT: [[X2:%.*]] = and i32 %x, [[NEGX]]
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; CHECK-NEXT: [[E:%.*]] = zext i32 [[X2]] to i64
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; CHECK-NEXT: ret i64 [[E]]
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;
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%negx = sub i32 0, %x
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%x2 = and i32 %x, %negx
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%e = zext i32 %x2 to i64
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%nege = sub i64 0, %e
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%e2 = and i64 %e, %nege
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ret i64 %e2
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}
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define i64 @pow2b(i32 %x) {
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; CHECK-LABEL: @pow2b(
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; CHECK-NEXT: [[SH:%.*]] = shl i32 2, %x
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; CHECK-NEXT: [[E:%.*]] = zext i32 [[SH]] to i64
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; CHECK-NEXT: ret i64 [[E]]
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;
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%sh = shl i32 2, %x
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%e = zext i32 %sh to i64
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%nege = sub i64 0, %e
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%e2 = and i64 %e, %nege
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ret i64 %e2
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}
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define i32 @sub_neg_nuw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_neg_nuw(
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; CHECK-NEXT: ret i32 %x
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;
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%neg = sub nuw i32 0, %y
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%sub = sub i32 %x, %neg
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ret i32 %sub
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}
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define i1 @and_of_icmps0(i32 %b) {
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; CHECK-LABEL: @and_of_icmps0(
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; CHECK-NEXT: ret i1 false
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;
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%1 = add i32 %b, 2
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%2 = icmp ult i32 %1, 4
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @and_of_icmps1(i32 %b) {
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; CHECK-LABEL: @and_of_icmps1(
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp slt i32 %1, 4
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @and_of_icmps2(i32 %b) {
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; CHECK-LABEL: @and_of_icmps2(
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; CHECK-NEXT: ret i1 false
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;
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%1 = add i32 %b, 2
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%2 = icmp ule i32 %1, 3
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @and_of_icmps3(i32 %b) {
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; CHECK-LABEL: @and_of_icmps3(
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp sle i32 %1, 3
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @and_of_icmps4(i32 %b) {
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; CHECK-LABEL: @and_of_icmps4(
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp ult i32 %1, 4
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%cmp3 = icmp ugt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @and_of_icmps5(i32 %b) {
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; CHECK-LABEL: @and_of_icmps5(
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp ule i32 %1, 3
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%cmp3 = icmp ugt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @or_of_icmps0(i32 %b) {
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; CHECK-LABEL: @or_of_icmps0(
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; CHECK-NEXT: ret i1 true
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;
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%1 = add i32 %b, 2
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%2 = icmp uge i32 %1, 4
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @or_of_icmps1(i32 %b) {
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; CHECK-LABEL: @or_of_icmps1(
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp sge i32 %1, 4
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @or_of_icmps2(i32 %b) {
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; CHECK-LABEL: @or_of_icmps2(
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; CHECK-NEXT: ret i1 true
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;
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%1 = add i32 %b, 2
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%2 = icmp ugt i32 %1, 3
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @or_of_icmps3(i32 %b) {
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; CHECK-LABEL: @or_of_icmps3(
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp sgt i32 %1, 3
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @or_of_icmps4(i32 %b) {
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; CHECK-LABEL: @or_of_icmps4(
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp uge i32 %1, 4
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%cmp3 = icmp ule i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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}
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define i1 @or_of_icmps5(i32 %b) {
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; CHECK-LABEL: @or_of_icmps5(
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp ugt i32 %1, 3
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%cmp3 = icmp ule i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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}
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define i32 @neg_nuw(i32 %x) {
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; CHECK-LABEL: @neg_nuw(
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; CHECK-NEXT: ret i32 0
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;
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%neg = sub nuw i32 0, %x
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ret i32 %neg
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}
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define i1 @and_icmp1(i32 %x, i32 %y) {
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; CHECK-LABEL: @and_icmp1(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %x, %y
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = icmp ult i32 %x, %y
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%2 = icmp ne i32 %y, 0
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%3 = and i1 %1, %2
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ret i1 %3
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}
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define i1 @and_icmp2(i32 %x, i32 %y) {
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; CHECK-LABEL: @and_icmp2(
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; CHECK-NEXT: ret i1 false
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;
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%1 = icmp ult i32 %x, %y
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%2 = icmp eq i32 %y, 0
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%3 = and i1 %1, %2
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ret i1 %3
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}
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define i1 @or_icmp1(i32 %x, i32 %y) {
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; CHECK-LABEL: @or_icmp1(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 %y, 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = icmp ult i32 %x, %y
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%2 = icmp ne i32 %y, 0
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%3 = or i1 %1, %2
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ret i1 %3
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}
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define i1 @or_icmp2(i32 %x, i32 %y) {
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; CHECK-LABEL: @or_icmp2(
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; CHECK-NEXT: ret i1 true
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;
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%1 = icmp uge i32 %x, %y
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%2 = icmp ne i32 %y, 0
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%3 = or i1 %1, %2
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ret i1 %3
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}
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define i1 @or_icmp3(i32 %x, i32 %y) {
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; CHECK-LABEL: @or_icmp3(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 %x, %y
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = icmp uge i32 %x, %y
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%2 = icmp eq i32 %y, 0
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%3 = or i1 %1, %2
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ret i1 %3
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}
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define i1 @disjoint_cmps(i32 %A) {
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; CHECK-LABEL: @disjoint_cmps(
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; CHECK-NEXT: ret i1 false
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;
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%B = icmp eq i32 %A, 1
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%C = icmp sge i32 %A, 3
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%D = and i1 %B, %C
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ret i1 %D
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}
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define i1 @disjoint_cmps2(i32 %X) {
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; CHECK-LABEL: @disjoint_cmps2(
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; CHECK-NEXT: ret i1 false
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;
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%a = icmp ult i32 %X, 31
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%b = icmp slt i32 %X, 0
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%c = and i1 %a, %b
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ret i1 %c
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}
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; PR27869 - Look through casts to eliminate cmps and bitwise logic.
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define i32 @and_of_zexted_icmps(i32 %i) {
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; CHECK-LABEL: @and_of_zexted_icmps(
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; CHECK-NEXT: ret i32 0
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;
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%cmp0 = icmp eq i32 %i, 0
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%conv0 = zext i1 %cmp0 to i32
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%cmp1 = icmp ugt i32 %i, 4
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%conv1 = zext i1 %cmp1 to i32
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%and = and i32 %conv0, %conv1
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ret i32 %and
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}
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; Make sure vectors work too.
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define <4 x i32> @and_of_zexted_icmps_vec(<4 x i32> %i) {
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; CHECK-LABEL: @and_of_zexted_icmps_vec(
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; CHECK-NEXT: ret <4 x i32> zeroinitializer
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;
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%cmp0 = icmp eq <4 x i32> %i, zeroinitializer
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%conv0 = zext <4 x i1> %cmp0 to <4 x i32>
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%cmp1 = icmp slt <4 x i32> %i, zeroinitializer
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%conv1 = zext <4 x i1> %cmp1 to <4 x i32>
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%and = and <4 x i32> %conv0, %conv1
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ret <4 x i32> %and
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}
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; Try a different cast and weird types.
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define i5 @and_of_sexted_icmps(i3 %i) {
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; CHECK-LABEL: @and_of_sexted_icmps(
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; CHECK-NEXT: ret i5 0
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;
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%cmp0 = icmp eq i3 %i, 0
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%conv0 = sext i1 %cmp0 to i5
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%cmp1 = icmp ugt i3 %i, 1
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%conv1 = sext i1 %cmp1 to i5
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%and = and i5 %conv0, %conv1
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ret i5 %and
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}
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; Try a different cast and weird vector types.
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define i3 @and_of_bitcast_icmps_vec(<3 x i65> %i) {
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; CHECK-LABEL: @and_of_bitcast_icmps_vec(
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; CHECK-NEXT: ret i3 0
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;
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%cmp0 = icmp sgt <3 x i65> %i, zeroinitializer
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%conv0 = bitcast <3 x i1> %cmp0 to i3
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%cmp1 = icmp slt <3 x i65> %i, zeroinitializer
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%conv1 = bitcast <3 x i1> %cmp1 to i3
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%and = and i3 %conv0, %conv1
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ret i3 %and
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}
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; We can't do this if the casts are different.
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define i16 @and_of_different_cast_icmps(i8 %i) {
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; CHECK-LABEL: @and_of_different_cast_icmps(
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; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i8 %i, 0
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; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %i, 1
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; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
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; CHECK-NEXT: [[AND:%.*]] = and i16 [[CONV0]], [[CONV1]]
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; CHECK-NEXT: ret i16 [[AND]]
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;
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%cmp0 = icmp eq i8 %i, 0
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%conv0 = zext i1 %cmp0 to i16
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%cmp1 = icmp eq i8 %i, 1
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%conv1 = sext i1 %cmp1 to i16
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%and = and i16 %conv0, %conv1
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ret i16 %and
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}
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define <2 x i3> @and_of_different_cast_icmps_vec(<2 x i8> %i, <2 x i16> %j) {
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; CHECK-LABEL: @and_of_different_cast_icmps_vec(
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; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i8> %i, zeroinitializer
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; CHECK-NEXT: [[CONV0:%.*]] = zext <2 x i1> [[CMP0]] to <2 x i3>
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i16> %j, <i16 1, i16 1>
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; CHECK-NEXT: [[CONV1:%.*]] = zext <2 x i1> [[CMP1]] to <2 x i3>
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i3> [[CONV0]], [[CONV1]]
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; CHECK-NEXT: ret <2 x i3> [[AND]]
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;
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%cmp0 = icmp eq <2 x i8> %i, zeroinitializer
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%conv0 = zext <2 x i1> %cmp0 to <2 x i3>
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%cmp1 = icmp ugt <2 x i16> %j, <i16 1, i16 1>
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%conv1 = zext <2 x i1> %cmp1 to <2 x i3>
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%and = and <2 x i3> %conv0, %conv1
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ret <2 x i3> %and
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}
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