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a70016c8d5
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
204 lines
9.3 KiB
LLVM
204 lines
9.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}store_fi_lifetime:
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; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
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; GCN: buffer_store_dword [[FI]]
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define amdgpu_kernel void @store_fi_lifetime(i32 addrspace(1)* %out, i32 %in) #0 {
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entry:
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%b = alloca i8, addrspace(5)
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call void @llvm.lifetime.start.p5i8(i64 1, i8 addrspace(5)* %b)
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store volatile i8 addrspace(5)* %b, i8 addrspace(5)* addrspace(1)* undef
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call void @llvm.lifetime.end.p5i8(i64 1, i8 addrspace(5)* %b)
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_lds:
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; GCN: s_load_dword [[LDSPTR:s[0-9]+]]
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; GCN: buffer_store_dword v{{[0-9]+}}, off,
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; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 4{{$}}
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; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
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; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]]
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define amdgpu_kernel void @stored_fi_to_lds(float addrspace(5)* addrspace(3)* %ptr) #0 {
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%tmp = alloca float, addrspace(5)
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store float 4.0, float addrspace(5)*%tmp
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store float addrspace(5)* %tmp, float addrspace(5)* addrspace(3)* %ptr
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ret void
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}
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; Offset is applied
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; GCN-LABEL: {{^}}stored_fi_to_lds_2_small_objects:
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; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}}
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; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8{{$}}
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; GCN-DAG: s_load_dword [[LDSPTR:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
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; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO]]
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; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}}
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; GCN: ds_write_b32 [[VLDSPTR]], [[FI1]]
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define amdgpu_kernel void @stored_fi_to_lds_2_small_objects(float addrspace(5)* addrspace(3)* %ptr) #0 {
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%tmp0 = alloca float, addrspace(5)
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%tmp1 = alloca float, addrspace(5)
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store float 4.0, float addrspace(5)* %tmp0
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store float 4.0, float addrspace(5)* %tmp1
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store volatile float addrspace(5)* %tmp0, float addrspace(5)* addrspace(3)* %ptr
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store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(3)* %ptr
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ret void
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}
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; Same frame index is used multiple times in the store
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; GCN-LABEL: {{^}}stored_fi_to_self:
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x4d2{{$}}
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; GCN: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}}
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; GCN: buffer_store_dword [[ZERO]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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define amdgpu_kernel void @stored_fi_to_self() #0 {
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%tmp = alloca i32 addrspace(5)*, addrspace(5)
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; Avoid optimizing everything out
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store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp
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%bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp to i32 addrspace(5)*
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store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_self_offset:
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; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 32{{$}}
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; GCN: buffer_store_dword [[K0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x4d2{{$}}
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; GCN: buffer_store_dword [[K1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2052{{$}}
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; GCN: v_mov_b32_e32 [[OFFSETK:v[0-9]+]], 0x804{{$}}
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; GCN: buffer_store_dword [[OFFSETK]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2052{{$}}
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define amdgpu_kernel void @stored_fi_to_self_offset() #0 {
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%tmp0 = alloca [512 x i32], addrspace(5)
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%tmp1 = alloca i32 addrspace(5)*, addrspace(5)
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; Avoid optimizing everything out
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%tmp0.cast = bitcast [512 x i32] addrspace(5)* %tmp0 to i32 addrspace(5)*
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store volatile i32 32, i32 addrspace(5)* %tmp0.cast
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store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp1
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%bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp1 to i32 addrspace(5)*
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store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp1
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_fi:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12{{$}}
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; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}}
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; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12{{$}}
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; GCN: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}}
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; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8{{$}}
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define amdgpu_kernel void @stored_fi_to_fi() #0 {
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%tmp0 = alloca i32 addrspace(5)*, addrspace(5)
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%tmp1 = alloca i32 addrspace(5)*, addrspace(5)
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%tmp2 = alloca i32 addrspace(5)*, addrspace(5)
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store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp0
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store volatile i32 addrspace(5)* inttoptr (i32 5678 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp1
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store volatile i32 addrspace(5)* inttoptr (i32 9999 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp2
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%bitcast1 = bitcast i32 addrspace(5)* addrspace(5)* %tmp1 to i32 addrspace(5)*
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%bitcast2 = bitcast i32 addrspace(5)* addrspace(5)* %tmp2 to i32 addrspace(5)* ; at offset 8
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store volatile i32 addrspace(5)* %bitcast1, i32 addrspace(5)* addrspace(5)* %tmp2 ; store offset 4 at offset 8
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store volatile i32 addrspace(5)* %bitcast2, i32 addrspace(5)* addrspace(5)* %tmp1 ; store offset 8 at offset 4
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_global:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
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; GCN: buffer_store_dword [[FI]]
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define amdgpu_kernel void @stored_fi_to_global(float addrspace(5)* addrspace(1)* %ptr) #0 {
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%tmp = alloca float, addrspace(5)
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store float 0.0, float addrspace(5)*%tmp
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store float addrspace(5)* %tmp, float addrspace(5)* addrspace(1)* %ptr
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ret void
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}
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; Offset is applied
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; GCN-LABEL: {{^}}stored_fi_to_global_2_small_objects:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12{{$}}
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; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}}
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; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-DAG: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}}
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; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_kernel void @stored_fi_to_global_2_small_objects(float addrspace(5)* addrspace(1)* %ptr) #0 {
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%tmp0 = alloca float, addrspace(5)
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%tmp1 = alloca float, addrspace(5)
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%tmp2 = alloca float, addrspace(5)
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store volatile float 0.0, float addrspace(5)*%tmp0
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store volatile float 0.0, float addrspace(5)*%tmp1
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store volatile float 0.0, float addrspace(5)*%tmp2
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store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(1)* %ptr
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store volatile float addrspace(5)* %tmp2, float addrspace(5)* addrspace(1)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}stored_fi_to_global_huge_frame_offset:
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; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
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; FIXME: Re-initialize
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; GCN: v_mov_b32_e32 [[BASE_0_1:v[0-9]+]], 4{{$}}
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
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; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]]
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; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]]
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; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_kernel void @stored_fi_to_global_huge_frame_offset(i32 addrspace(5)* addrspace(1)* %ptr) #0 {
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%tmp0 = alloca [4096 x i32], addrspace(5)
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%tmp1 = alloca [4096 x i32], addrspace(5)
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%gep0.tmp0 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 0
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store volatile i32 0, i32 addrspace(5)* %gep0.tmp0
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%gep1.tmp0 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 4095
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store volatile i32 999, i32 addrspace(5)* %gep1.tmp0
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%gep0.tmp1 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 14
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store i32 addrspace(5)* %gep0.tmp1, i32 addrspace(5)* addrspace(1)* %ptr
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ret void
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}
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@g1 = external addrspace(1) global i32 addrspace(5)*
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; This was leaving a dead node around resulting in failing to select
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; on the leftover AssertZext's ValueType operand.
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; GCN-LABEL: {{^}}cannot_select_assertzext_valuetype:
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; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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; GCN: s_add_u32 s{{[0-9]+}}, s[[PC_LO]], g1@gotpcrel32@lo+4
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; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC_HI]], g1@gotpcrel32@hi+4
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; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
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; GCN: buffer_store_dword [[FI]]
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define amdgpu_kernel void @cannot_select_assertzext_valuetype(i32 addrspace(1)* %out, i32 %idx) #0 {
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entry:
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%b = alloca i32, align 4, addrspace(5)
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%tmp1 = load volatile i32 addrspace(5)*, i32 addrspace(5)* addrspace(1)* @g1, align 4
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%arrayidx = getelementptr inbounds i32, i32 addrspace(5)* %tmp1, i32 %idx
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%tmp2 = load i32, i32 addrspace(5)* %arrayidx, align 4
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store volatile i32 addrspace(5)* %b, i32 addrspace(5)* addrspace(1)* undef
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ret void
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}
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declare void @llvm.lifetime.start.p5i8(i64, i8 addrspace(5)* nocapture) #1
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declare void @llvm.lifetime.end.p5i8(i64, i8 addrspace(5)* nocapture) #1
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attributes #0 = { nounwind }
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attributes #1 = { argmemonly nounwind }
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