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llvm-mirror/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir
Eli Friedman 5c2a95ff67 [SelectionDAG][GISel] Make LegalizeDAG lower FNEG using integer ops.
Previously, if a floating-point type was legal, but FNEG wasn't legal,
we would use FSUB.  Instead, we should use integer ops, to preserve the
semantics.  (Alternatively, there's a compiler-rt call we could use, but
there isn't much reason to use that.)

It turns out we actually are still using this obscure codepath in a few
cases: on some targets, we have "legal" floating-point types that don't
actually support any floating-point operations.  In particular, ARM and
AArch64 are using this path.

The implementation for SelectionDAG is pretty simple because we can
reuse the infrastructure from FCOPYSIGN.

See also 9a3dc3e, the corresponding change to type legalization.

Also includes a "bonus" change to STRICT_FSUB legalization, so we can
lower a STRICT_FSUB to a float libcall.

Includes the changes to both LegalizeDAG and GlobalISel so we don't have
inconsistent results in the future.

Fixes https://bugs.llvm.org/show_bug.cgi?id=46792 .

Differential Revision: https://reviews.llvm.org/D84287
2020-09-23 14:10:33 -07:00

870 lines
22 KiB
YAML

# RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
--- |
define void @test_add_s8() { ret void }
define void @test_add_s16() { ret void }
define void @test_add_s32() { ret void }
define void @test_sub_s8() { ret void }
define void @test_sub_s16() { ret void }
define void @test_sub_s32() { ret void }
define void @test_mul_s8() { ret void }
define void @test_mul_s16() { ret void }
define void @test_mul_s32() { ret void }
define void @test_and_s8() { ret void }
define void @test_and_s16() { ret void }
define void @test_and_s32() { ret void }
define void @test_and_s64() { ret void }
define void @test_or_s8() { ret void }
define void @test_or_s16() { ret void }
define void @test_or_s32() { ret void }
define void @test_or_s64() { ret void }
define void @test_xor_s8() { ret void }
define void @test_xor_s16() { ret void }
define void @test_xor_s32() { ret void }
define void @test_xor_s64() { ret void }
define void @test_lshr_s32() { ret void }
define void @test_ashr_s32() { ret void }
define void @test_shl_s32() { ret void }
define void @test_shift_s8() { ret void }
define void @test_shift_s16() { ret void }
define void @test_shift_amount_s8() { ret void }
define void @test_shift_amount_s16() { ret void }
...
---
name: test_add_s8
# CHECK-LABEL: name: test_add_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
%2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_ADD %1, %3
; G_ADD with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s16
# CHECK-LABEL: name: test_add_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_ADD %1, %3
; G_ADD with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_ADD %0, %1
; G_ADD with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_s8
# CHECK-LABEL: name: test_sub_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
%2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_SUB %1, %3
; G_SUB with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_s16
# CHECK-LABEL: name: test_sub_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_SUB %1, %3
; G_SUB with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_SUB %0, %1
; G_SUB with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s8
# CHECK-LABEL: name: test_mul_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
%2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_MUL %1, %3
; G_MUL with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s16
# CHECK-LABEL: name: test_mul_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_MUL %1, %3
; G_MUL with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s32
# CHECK-LABEL: name: test_mul_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_MUL %0, %1
; G_MUL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s8
# CHECK-LABEL: name: test_and_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
%2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_AND %1, %3
; G_AND with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s16
# CHECK-LABEL: name: test_and_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_AND %1, %3
; G_AND with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s32
# CHECK-LABEL: name: test_and_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_AND %0, %1
; G_AND with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s64
# CHECK-LABEL: name: test_and_s64
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = COPY $r2
%3(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%6(s64) = G_AND %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
$r0 = COPY %7(s32)
$r1 = COPY %8(s32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_or_s8
# CHECK-LABEL: name: test_or_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
%2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_OR %1, %3
; G_OR with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_or_s16
# CHECK-LABEL: name: test_or_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_OR %1, %3
; G_OR with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_or_s32
# CHECK-LABEL: name: test_or_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_OR %0, %1
; G_OR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_or_s64
# CHECK-LABEL: name: test_or_s64
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = COPY $r2
%3(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%6(s64) = G_OR %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
$r0 = COPY %7(s32)
$r1 = COPY %8(s32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_xor_s8
# CHECK-LABEL: name: test_xor_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
%2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_XOR %1, %3
; G_XOR with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_xor_s16
# CHECK-LABEL: name: test_xor_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_XOR %1, %3
; G_XOR with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
$r0 = COPY %5(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_xor_s32
# CHECK-LABEL: name: test_xor_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_XOR %0, %1
; G_XOR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_xor_s64
# CHECK-LABEL: name: test_xor_s64
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = COPY $r2
%3(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%6(s64) = G_XOR %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
$r0 = COPY %7(s32)
$r1 = COPY %8(s32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_LSHR %0, %1
; G_LSHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_ashr_s32
# CHECK-LABEL: name: test_ashr_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_ASHR %0, %1
; G_ASHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_shl_s32
# CHECK-LABEL: name: test_shl_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s32) = G_SHL %0, %1
; G_SHL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_shift_s8
# CHECK-LABEL: name: test_shift_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s8) = G_TRUNC %0(s32)
%3(s8) = G_SHL %2, %1(s32)
; G_SHL with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SHL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SHL {{%[0-9]+, %[0-9]+}}
%4(s32) = G_SEXT %3(s8)
$r0 = COPY %4(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_shift_s16
# CHECK-LABEL: name: test_shift_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s16) = G_TRUNC %0(s32)
%3(s16) = G_SHL %2, %1(s32)
; G_SHL with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SHL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SHL {{%[0-9]+, %[0-9]+}}
%4(s32) = G_SEXT %3(s16)
$r0 = COPY %4(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_shift_amount_s8
# CHECK-LABEL: name: test_shift_amount_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s8) = G_TRUNC %0(s32)
%3(s32) = G_SHL %1, %2(s8)
; G_SHL with s8 amount should widen
; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s8)
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s32)
; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s8)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_shift_amount_s16
# CHECK-LABEL: name: test_shift_amount_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0:
liveins: $r0, $r1
%0(s32) = COPY $r0
%1(s32) = COPY $r1
%2(s16) = G_TRUNC %0(s32)
%3(s32) = G_SHL %1, %2(s16)
; G_SHL with s16 amount should widen
; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s16)
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s32)
; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s16)
$r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0
...