mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
bbf5be9d55
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
315 lines
11 KiB
YAML
315 lines
11 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_icmp_eq_s32() { ret void }
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define void @test_icmp_ne_s32() { ret void }
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define void @test_icmp_ugt_s32() { ret void }
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define void @test_icmp_uge_s32() { ret void }
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define void @test_icmp_ult_s32() { ret void }
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define void @test_icmp_ule_s32() { ret void }
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define void @test_icmp_sgt_s32() { ret void }
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define void @test_icmp_sge_s32() { ret void }
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define void @test_icmp_slt_s32() { ret void }
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define void @test_icmp_sle_s32() { ret void }
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...
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---
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name: test_icmp_eq_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_eq_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 0 /* CC::eq */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(eq), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_ne_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_ne_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 1 /* CC::ne */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(ne), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_ugt_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_ugt_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 8 /* CC::hi */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_uge_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_uge_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 2 /* CC::hs */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(uge), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_ult_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_ult_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 3 /* CC::lo */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(ult), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_ule_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_ule_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 9 /* CC::ls */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(ule), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_sgt_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_sgt_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 12 /* CC::gt */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_sge_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_sge_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 10 /* CC::ge */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(sge), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_slt_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_slt_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 11 /* CC::lt */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(slt), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_icmp_sle_s32
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_icmp_sle_s32
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 13 /* CC::le */, $cpsr
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_ICMP intpred(sle), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$r0 = COPY %3(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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