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129 lines
4.1 KiB
LLVM
129 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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@x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
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@y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
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; Besides anything else, these tests help verify that libcall ABI lowering
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; works correctly
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define i32 @test_load_and_cmp() nounwind {
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; RV32I-LABEL: test_load_and_cmp:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -48
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; RV32I-NEXT: sw ra, 44(sp)
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; RV32I-NEXT: lui a0, %hi(y+12)
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; RV32I-NEXT: addi a0, a0, %lo(y+12)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 20(sp)
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; RV32I-NEXT: lui a0, %hi(y+8)
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; RV32I-NEXT: addi a0, a0, %lo(y+8)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 16(sp)
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; RV32I-NEXT: lui a0, %hi(y+4)
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; RV32I-NEXT: addi a0, a0, %lo(y+4)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 12(sp)
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; RV32I-NEXT: lui a0, %hi(y)
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; RV32I-NEXT: addi a0, a0, %lo(y)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 8(sp)
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; RV32I-NEXT: lui a0, %hi(x+12)
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; RV32I-NEXT: addi a0, a0, %lo(x+12)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 36(sp)
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; RV32I-NEXT: lui a0, %hi(x+8)
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; RV32I-NEXT: addi a0, a0, %lo(x+8)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 32(sp)
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; RV32I-NEXT: lui a0, %hi(x+4)
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; RV32I-NEXT: addi a0, a0, %lo(x+4)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 28(sp)
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; RV32I-NEXT: lui a0, %hi(x)
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; RV32I-NEXT: addi a0, a0, %lo(x)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 24(sp)
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; RV32I-NEXT: lui a0, %hi(__netf2)
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; RV32I-NEXT: addi a2, a0, %lo(__netf2)
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; RV32I-NEXT: addi a0, sp, 24
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; RV32I-NEXT: addi a1, sp, 8
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; RV32I-NEXT: jalr a2
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; RV32I-NEXT: xor a0, a0, zero
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: lw ra, 44(sp)
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; RV32I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: ret
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%1 = load fp128, fp128* @x, align 16
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%2 = load fp128, fp128* @y, align 16
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%cmp = fcmp une fp128 %1, %2
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%3 = zext i1 %cmp to i32
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ret i32 %3
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}
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define i32 @test_add_and_fptosi() nounwind {
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; RV32I-LABEL: test_add_and_fptosi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -80
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; RV32I-NEXT: sw ra, 76(sp)
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; RV32I-NEXT: lui a0, %hi(y+12)
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; RV32I-NEXT: addi a0, a0, %lo(y+12)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 36(sp)
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; RV32I-NEXT: lui a0, %hi(y+8)
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; RV32I-NEXT: addi a0, a0, %lo(y+8)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 32(sp)
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; RV32I-NEXT: lui a0, %hi(y+4)
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; RV32I-NEXT: addi a0, a0, %lo(y+4)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 28(sp)
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; RV32I-NEXT: lui a0, %hi(y)
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; RV32I-NEXT: addi a0, a0, %lo(y)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 24(sp)
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; RV32I-NEXT: lui a0, %hi(x+12)
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; RV32I-NEXT: addi a0, a0, %lo(x+12)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 52(sp)
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; RV32I-NEXT: lui a0, %hi(x+8)
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; RV32I-NEXT: addi a0, a0, %lo(x+8)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 48(sp)
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; RV32I-NEXT: lui a0, %hi(x+4)
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; RV32I-NEXT: addi a0, a0, %lo(x+4)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 44(sp)
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; RV32I-NEXT: lui a0, %hi(x)
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; RV32I-NEXT: addi a0, a0, %lo(x)
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: sw a0, 40(sp)
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; RV32I-NEXT: lui a0, %hi(__addtf3)
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; RV32I-NEXT: addi a3, a0, %lo(__addtf3)
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; RV32I-NEXT: addi a0, sp, 56
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; RV32I-NEXT: addi a1, sp, 40
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; RV32I-NEXT: addi a2, sp, 24
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; RV32I-NEXT: jalr a3
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; RV32I-NEXT: lw a0, 68(sp)
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; RV32I-NEXT: sw a0, 20(sp)
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; RV32I-NEXT: lw a0, 64(sp)
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; RV32I-NEXT: sw a0, 16(sp)
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; RV32I-NEXT: lw a0, 60(sp)
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; RV32I-NEXT: sw a0, 12(sp)
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; RV32I-NEXT: lw a0, 56(sp)
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; RV32I-NEXT: sw a0, 8(sp)
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; RV32I-NEXT: lui a0, %hi(__fixtfsi)
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; RV32I-NEXT: addi a1, a0, %lo(__fixtfsi)
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; RV32I-NEXT: addi a0, sp, 8
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; RV32I-NEXT: jalr a1
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; RV32I-NEXT: lw ra, 76(sp)
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; RV32I-NEXT: addi sp, sp, 80
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; RV32I-NEXT: ret
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%1 = load fp128, fp128* @x, align 16
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%2 = load fp128, fp128* @y, align 16
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%3 = fadd fp128 %1, %2
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%4 = fptosi fp128 %3 to i32
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ret i32 %4
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}
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