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52 lines
1.5 KiB
LLVM
52 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; Basic shift support is tested as part of ALU.ll. This file ensures that
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; shifts which may not be supported natively are lowered properly.
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define i64 @lshr64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: lshr64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a3, %hi(__lshrdi3)
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; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3)
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; RV32I-NEXT: jalr a3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = lshr i64 %a, %b
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ret i64 %1
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}
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define i64 @ashr64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: ashr64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a3, %hi(__ashrdi3)
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; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3)
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; RV32I-NEXT: jalr a3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = ashr i64 %a, %b
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ret i64 %1
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}
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define i64 @shl64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: shl64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: lui a3, %hi(__ashldi3)
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; RV32I-NEXT: addi a3, a3, %lo(__ashldi3)
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; RV32I-NEXT: jalr a3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = shl i64 %a, %b
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ret i64 %1
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}
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