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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
34 lines
1.7 KiB
LLVM
34 lines
1.7 KiB
LLVM
; RUN: llc < %s -mcpu=generic | FileCheck %s
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; PR6941
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.0.0"
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define i32 @snd_xbytes(i32 %v, i32 %from, i32 %to) nounwind readnone ssp {
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entry:
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%cmp19 = icmp eq i32 %to, 0 ; <i1> [#uses=1]
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br i1 %cmp19, label %while.end, label %while.cond
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while.cond: ; preds = %entry, %while.cond
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%y.021 = phi i32 [ %rem, %while.cond ], [ %to, %entry ] ; <i32> [#uses=3]
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%x.020 = phi i32 [ %y.021, %while.cond ], [ %from, %entry ] ; <i32> [#uses=1]
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%rem = urem i32 %x.020, %y.021 ; <i32> [#uses=2]
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%cmp = icmp eq i32 %rem, 0 ; <i1> [#uses=1]
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br i1 %cmp, label %while.end, label %while.cond
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while.end: ; preds = %while.cond, %entry
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%x.0.lcssa = phi i32 [ %from, %entry ], [ %y.021, %while.cond ] ; <i32> [#uses=2]
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%div = udiv i32 %from, %x.0.lcssa ; <i32> [#uses=1]
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%div11 = udiv i32 %to, %x.0.lcssa ; <i32> [#uses=1]
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%conv = zext i32 %v to i64 ; <i64> [#uses=1]
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%conv14 = zext i32 %div11 to i64 ; <i64> [#uses=1]
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; Verify that we don't clobber %eax after putting the imulq result in %rax
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; CHECK: imulq %r{{.}}x, %r[[RES:..]]
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; CHECK-NOT: movl {{.*}}, %e[[RES]]
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; CHECK: div
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%mul = mul i64 %conv14, %conv ; <i64> [#uses=1]
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%conv16 = zext i32 %div to i64 ; <i64> [#uses=1]
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%div17 = udiv i64 %mul, %conv16 ; <i64> [#uses=1]
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%conv18 = trunc i64 %div17 to i32 ; <i32> [#uses=1]
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ret i32 %conv18
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}
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