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e3e67d4a0a
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
45 lines
1.1 KiB
LLVM
45 lines
1.1 KiB
LLVM
; RUN: llc < %s -tailcallopt -mtriple=i686-linux-gnu | FileCheck %s
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; Test the GHC call convention works (x86-32)
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@base = external global i32 ; assigned to register: EBX
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@sp = external global i32 ; assigned to register: EBP
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@hp = external global i32 ; assigned to register: EDI
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@r1 = external global i32 ; assigned to register: ESI
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define void @zap(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: movl {{[0-9]*}}(%esp), %ebx
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; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp
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; CHECK-NEXT: calll addtwo
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%0 = call cc 10 i32 @addtwo(i32 %a, i32 %b)
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; CHECK: calll foo
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call void @foo() nounwind
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ret void
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}
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define cc 10 i32 @addtwo(i32 %x, i32 %y) nounwind {
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entry:
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; CHECK: leal (%ebx,%ebp), %eax
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%0 = add i32 %x, %y
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; CHECK-NEXT: ret
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ret i32 %0
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}
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define cc 10 void @foo() nounwind {
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entry:
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; CHECK: movl r1, %esi
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; CHECK-NEXT: movl hp, %edi
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; CHECK-NEXT: movl sp, %ebp
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; CHECK-NEXT: movl base, %ebx
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%0 = load i32* @r1
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%1 = load i32* @hp
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%2 = load i32* @sp
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%3 = load i32* @base
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; CHECK: jmp bar
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tail call cc 10 void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind
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ret void
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}
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declare cc 10 void @bar(i32, i32, i32, i32)
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