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5f6f8101d5
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
45 lines
1.5 KiB
LLVM
45 lines
1.5 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats |& not grep {Number of register spills}
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define fastcc void @fourn(double* %data, i32 %isign) nounwind {
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entry:
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br label %bb
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bb: ; preds = %bb, %entry
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%indvar93 = phi i32 [ 0, %entry ], [ %idim.030, %bb ] ; <i32> [#uses=2]
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%idim.030 = add i32 %indvar93, 1 ; <i32> [#uses=1]
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%0 = add i32 %indvar93, 2 ; <i32> [#uses=1]
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%1 = icmp sgt i32 %0, 2 ; <i1> [#uses=1]
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br i1 %1, label %bb30.loopexit, label %bb
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bb3: ; preds = %bb30.loopexit, %bb25, %bb3
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%2 = load i32* null, align 4 ; <i32> [#uses=1]
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%3 = mul i32 %2, 0 ; <i32> [#uses=1]
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%4 = icmp slt i32 0, %3 ; <i1> [#uses=1]
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br i1 %4, label %bb18, label %bb3
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bb18: ; preds = %bb3
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%5 = fdiv double %11, 0.000000e+00 ; <double> [#uses=1]
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%6 = tail call double @sin(double %5) nounwind readonly ; <double> [#uses=1]
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br label %bb24.preheader
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bb22.preheader: ; preds = %bb24.preheader, %bb22.preheader
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br label %bb22.preheader
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bb25: ; preds = %bb24.preheader
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%7 = fmul double 0.000000e+00, %6 ; <double> [#uses=0]
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%8 = add i32 %i3.122100, 0 ; <i32> [#uses=1]
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%9 = icmp sgt i32 %8, 0 ; <i1> [#uses=1]
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br i1 %9, label %bb3, label %bb24.preheader
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bb24.preheader: ; preds = %bb25, %bb18
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%i3.122100 = or i32 0, 1 ; <i32> [#uses=2]
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%10 = icmp slt i32 0, %i3.122100 ; <i1> [#uses=1]
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br i1 %10, label %bb25, label %bb22.preheader
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bb30.loopexit: ; preds = %bb
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%11 = fmul double 0.000000e+00, 0x401921FB54442D1C ; <double> [#uses=1]
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br label %bb3
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}
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declare double @sin(double) nounwind readonly
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