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8d48a252a1
The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
61 lines
1.6 KiB
LLVM
61 lines
1.6 KiB
LLVM
; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s
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; CHECK-LABEL: qadd
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define i32 @qadd() nounwind {
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; CHECK: mov [[R0:.*]], #8
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; CHECK: mov [[R1:.*]], #128
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; CHECK: qadd [[R0]], [[R1]], [[R0]]
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%tmp = call i32 @llvm.arm.qadd(i32 128, i32 8)
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ret i32 %tmp
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}
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; CHECK-LABEL: qsub
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define i32 @qsub() nounwind {
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; CHECK: mov [[R0:.*]], #8
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; CHECK: mov [[R1:.*]], #128
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; CHECK: qsub [[R0]], [[R1]], [[R0]]
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%tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
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ret i32 %tmp
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}
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; upper-bound of the immediate argument
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; CHECK-LABEL: ssat1
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define i32 @ssat1() nounwind {
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; CHECK: mov [[R0:.*]], #128
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; CHECK: ssat [[R1:.*]], #32, [[R0]]
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%tmp = call i32 @llvm.arm.ssat(i32 128, i32 32)
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ret i32 %tmp
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}
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; lower-bound of the immediate argument
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; CHECK-LABEL: ssat2
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define i32 @ssat2() nounwind {
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; CHECK: mov [[R0:.*]], #128
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; CHECK: ssat [[R1:.*]], #1, [[R0]]
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%tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
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ret i32 %tmp
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}
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; upper-bound of the immediate argument
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; CHECK-LABEL: usat1
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define i32 @usat1() nounwind {
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; CHECK: mov [[R0:.*]], #128
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; CHECK: usat [[R1:.*]], #31, [[R0]]
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%tmp = call i32 @llvm.arm.usat(i32 128, i32 31)
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ret i32 %tmp
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}
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; lower-bound of the immediate argument
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; CHECK-LABEL: usat2
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define i32 @usat2() nounwind {
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; CHECK: mov [[R0:.*]], #128
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; CHECK: usat [[R1:.*]], #0, [[R0]]
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%tmp = call i32 @llvm.arm.usat(i32 128, i32 0)
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ret i32 %tmp
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}
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declare i32 @llvm.arm.qadd(i32, i32) nounwind
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declare i32 @llvm.arm.qsub(i32, i32) nounwind
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declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
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declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
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