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648fe59146
This includes
Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall
mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0,
Assembler directives: .set virt, .set novirt, .module virt, .module novirt
Attribute: virt
.MIPS.abiflags: VZ (0x100)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44905
llvm-svn: 331024
10 lines
376 B
ArmAsm
10 lines
376 B
ArmAsm
# RUN: not llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
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# RUN: -mcpu=mips32r5 -mattr=+virt 2>%t1
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# RUN: FileCheck %s < %t1
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
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# RUN: -mcpu=mips64r5 -mattr=+virt 2>%t1
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# RUN: FileCheck %s < %t1
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.set novirt
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hypcall # CHECK: instruction requires a CPU feature not currently enabled
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