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8ccbd5af71
v7M only allows the 16-bit encoding of the 'cps' (Change Processor State) instruction, and does not have the 32-bit encoding which is valid from v6T2 onwards. llvm-svn: 218382
18 lines
849 B
ArmAsm
18 lines
849 B
ArmAsm
@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
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cpsie f
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cpsie i, #3
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cps #0
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@ CHECK: cpsie f @ encoding: [0x61,0xb6]
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@ CHECK: cpsie i, #3 @ encoding: [0xaf,0xf3,0x43,0x85]
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@ CHECK: cps #0 @ encoding: [0xaf,0xf3,0x00,0x81]
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@ UNDEF-DAG: cpsie f @ encoding: [0x61,0xb6]
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@ UNDEF-DAG: error: instruction requires:
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@ UNDEF-DAG: error: instruction 'cps' requires effect for M-class
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