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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-31 07:52:55 +01:00
llvm-mirror/test/CodeGen
2011-05-18 19:59:50 +00:00
..
Alpha
ARM In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 2011-05-18 06:42:21 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic Move test for appropriate directory. 2011-05-17 19:06:43 +00:00
MBlaze
Mips Remove LLVM IR metadata in test case committed in r130847. 2011-05-04 18:28:36 +00:00
MSP430 Fix register-dependent test in MSP430. 2011-05-04 01:01:39 +00:00
PowerPC FileCheckize and break dependence on coalescing order. 2011-05-04 19:02:01 +00:00
PTX PTX: add flag to disable mad/fma selection 2011-05-18 15:42:23 +00:00
SPARC Fix more register and coalescing dependencies. 2011-05-04 19:02:11 +00:00
SystemZ
Thumb Move this test to CodeGen/Thumb. rdar://problem/9416774 2011-05-11 19:41:28 +00:00
Thumb2 Since I can't reproduce the failures from 131261, re-trying with a 2011-05-13 00:51:54 +00:00
X86 Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. 2011-05-18 19:59:50 +00:00
XCore Fix register-dependent XCore tests 2011-05-04 01:01:41 +00:00